STT-MRAM Gate Logic for Non-Volatile Reconfiguration
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Solution Overview
Problem
Current programmable logic devices, such as FPGAs, are inefficient in terms of power usage and scalability, particularly for battery-powered devices, and lack reconfigurable logic capabilities using non-volatile magnetic memory elements.
Innovation Solution
The use of spin torque transfer (STT) MRAM elements to implement reprogrammable logic functions, allowing for dynamic reconfiguration of logic operations without changing the topology, and enabling efficient write-programming with lower current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FPGAs are used for reprogrammable logic, then logic reconfiguration capability is achieved, but power consumption increases and scalability to higher device pitch density is limited
Solution Approach 1:
The patent replaces conventional CMOS-based FPGA logic elements with magnetic tunnel junction (MTJ) based logic elements. The MTJ devices use spin transfer torque to switch magnetization states, substituting the electrical field-effect mechanism with a magnetic mechanism that consumes less power during switching operations and maintains state without continuous power supply.
Solution Approach 2:
The patent changes the fundamental operating parameter from electrical voltage control in CMOS to magnetic moment orientation in MTJ devices. By utilizing the resistance difference between parallel and anti-parallel magnetization states, the logic elements achieve reconfiguration through magnetic field or current-induced switching rather than voltage threshold switching, reducing static power consumption.
2Reliability
If conventional MRAM is used for memory storage, then non-volatile storage is achieved, but switching power levels are too high for battery-powered devices and scaling to higher device pitch density is difficult
Solution Approach 1:
The patent segments the MRAM cell structure into a shared bit line configuration where multiple MTJ devices share common bit lines. This segmentation allows for reduced current requirements per device while maintaining non-volatile storage capability, as the switching current is distributed and managed through the shared interconnect structure.
Solution Approach 2:
The patent makes the MTJ devices serve dual functions: they act as both memory storage elements (retaining state without power) and as logic circuit elements (performing logical operations through resistance-based logic). This multi-functionality eliminates the need for separate memory and logic blocks, reducing overall power consumption and enabling scaling to higher device pitch densities.
3Adaptability or versatility
If generic chip architecture with both AND and OR gates is used, then various logic functions can be implemented, but chip space is wasted with unused components
Solution Approach 1:
The patent implements universal logic elements based on MTJ devices that can be configured to perform different logic functions (AND, OR, NAND, NOR, XOR, etc.) by changing the resistance states of the MTJ devices. This reconfigurability allows a single generic array of logic elements to replace dedicated AND and OR gate arrays, achieving full logic functionality without requiring both gate types to be physically present on the chip.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability where the logic function of each element can be changed after manufacturing by programming the resistance states of the MTJ devices. This dynamic adaptability allows the chip architecture to be optimized for specific applications, eliminating the need for fixed generic architectures that waste chip space with unused logic components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a scalable, power-efficient, and non-volatile reprogrammable logic device that retains configuration when powered off and supports various logic operations like AND, OR, NAND, and NOR gates, optimizing chip space usage and reducing standby power consumption.
Implementation Method 1
The free layer is programmed by means of spin torque transfer of the electron spin polarization of the write current going directly through the junction
Implementation Method 2
Magnetoresistance random access memory (MRAM) is a memory element base on the tunneling resistance of an oxide sandwiched between two magnetic layers. When the magnetization in the two layers are parallel, the tunneling resistance is 'low,' and this is referred to as a State 0. When the magnetization in the two layers are anti-parallel, the tunneling resistance is 'high,' and this is referred to as a State 1.
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
A re-programmable gate logic (400) includes a plurality of non-volatile re-configurable resistance state-based memory circuits (I) in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal (A, B). An evaluation switch (418) in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal (420) based on the programmed states of the memory circuits. A sensor (430) is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.