STT-MRAM Reference Resistance Setting for Accurate OTP Readout
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Solution Overview
Problem
Existing memory devices, particularly magnetic memory devices like STT-MRAM, face challenges in ensuring product reliability and data integrity, especially in highly integrated and nonvolatile applications such as OTP memory, which requires precise resistance settings for accurate data reading.
Innovation Solution
The proposed memory device incorporates a controller with a reference resistance setting module that detects resistance distributions in both memory and OTP cells, setting optimal reference resistances for accurate data reading and error correction, using magnetic tunnel junction elements and transistors to isolate read and write paths in OTP cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference resistance is used for both memory cells and OTP cells, then device complexity is reduced, but measurement precision deteriorates due to resistance distribution variations
Solution Approach 1:
The reference resistance configuration is segmented into two distinct types: first reference resistors for memory cells and second reference resistors for OTP cells. This segmentation allows each reference resistance to be optimized for its specific cell type, improving measurement precision while maintaining manageable device complexity through systematic organization.
Solution Approach 2:
Different reference resistance values are assigned to different cell types based on their specific resistance distributions. Memory cells use first reference resistors with values optimized for their resistance characteristics, while OTP cells use second reference resistors optimized for their distinct resistance profile, ensuring local optimization of measurement precision.
2Device complexity
If OTP cells share write path with memory cells, then device complexity is reduced, but reliability deteriorates due to interference between programming operations
Solution Approach 1:
The write path is segmented into separate channels: memory cells have dedicated write paths through specific word lines and bit lines, while OTP cells have isolated write paths through separate word lines (WL_O_1, WL_O2, WL_O3). This segmentation prevents interference between volatile and non-volatile programming operations, ensuring data integrity.
Solution Approach 2:
Separate word lines act as intermediaries that isolate the programming operations of OTP cells from memory cells. The dedicated word lines for OTP cells prevent direct interference with memory cell operations during programming, while still allowing both cell types to coexist in the same memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances product reliability by improving data integrity and accuracy in reading operations, ensuring stable and secure data storage in highly integrated memory devices.
Implementation Method 1
STT-M RAM (spin transfer torque magnetoresistive random-access memory) which stores therein information using the Spin Transfer Torque (STT) phenomenon, is being studied. The STT-MRAM may store therein information by directly applying current to a magnetic tunnel junction element to induce magnetization reversal.
Implementation Method 2
a memory cell including a first magnetic tunnel junction element; an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element
Data Source
AI summary
A memory device is provided. The memory device includes a nonvolatile memory including a memory cell array, and a controller configured to control the nonvolatile memory. The memory cell array includes: a memory cell including a first magnetic tunnel junction element, an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element, and a reference cell connected to a first reference resistor for reading data for the memory cell or a second reference resistor for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance.