STT-MRAM Cell Area Reduction via 3D Pillar Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing structure of spin-transfer torque magnetoresistive random access memory (STT-MRAM) arrays requires a large area for bit-cell arrays due to the parallel arrangement of source lines and word lines, leading to increased bit-cell dimensions and inefficiencies in memory cell layout.
Innovation Solution
A semiconductor device with a magnetic tunnel junction storage element is designed, featuring pillar-shaped semiconductor layers, gate insulating films, and source and bit lines arranged in a hierarchical structure, allowing for reduced cell area by sharing a single source line among multiple memory cells and eliminating the need for deep contacts between pillar-shaped and fin-shaped semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source lines are arranged parallel to word lines in a planar transistor structure, then the memory device can be manufactured using conventional processes, but the bit-cell area increases and bit-cell dimensions become large
Solution Approach 1:
The invention transitions from a planar two-dimensional layout to a three-dimensional vertical structure by arranging source lines, bit lines, and word lines in different vertical layers. The pillar-shaped semiconductor layer extends vertically from the substrate, with gate lines wrapping around it, allowing source and bit lines to be positioned at different heights rather than competing for the same planar space. This dimensional change enables higher density without sacrificing manufacturability.
Solution Approach 2:
The gate line is configured to surround and wrap around the pillar-shaped semiconductor layer, creating a nested structure where the gate electrode encloses the semiconductor pillar. This nested arrangement allows the gate to control the semiconductor channel from multiple sides, improving control efficiency while maintaining a compact footprint that reduces bit-cell area.
2Area of stationary object
If a surrounding gate transistor structure with pillar-shaped semiconductor layers is used, then the bit-cell area is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct sequential stages: first forming the fin-shaped semiconductor layer and insulating films, then depositing and patterning polysilicon to create the pillar-shaped semiconductor layer and dummy gates, followed by selective removal of dummy gates and formation of gate lines. This segmentation of the complex manufacturing process into manageable steps reduces overall process complexity while achieving the compact three-dimensional structure.
Solution Approach 2:
Dummy gates are introduced as intermediary structures during manufacturing. These temporary polysilicon structures serve as placeholders that guide the formation of the final gate line configuration. The dummy gates are formed, used to define the gate line pattern, and then selectively removed, simplifying the overall manufacturing sequence by providing a clear intermediate step rather than attempting to form the complex gate structure in a single operation.
3Reliability
If deep contacts are formed between pillar-shaped and fin-shaped semiconductor layers, then electrical connection is achieved, but manufacturing difficulty and misalignment risk increase
Solution Approach 1:
The fin-shaped semiconductor layer and its associated insulating films are formed in advance as a prepared substrate structure before the pillar-shaped semiconductor layer is created. This preliminary formation establishes a stable foundation with pre-defined contact regions, ensuring that subsequent pillar formation and contact creation can proceed with improved alignment accuracy, as the target locations are already prepared and marked by the underlying fin structure.
Data Source
AI summary
A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.