STT-MRAM Power Gating Transistor for Leakage Reduction
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Solution Overview
Problem
Current Spin Transfer Torque-Magnetoresistive Random Access Memories (STT-MRAM) face challenges with high access time, cycle time, and inefficiency due to the large size of the grain used for power gating, which complicates the structure and increases occupied area, making high integration difficult.
Innovation Solution
A memory cell design that includes a flip-flop based on magnetic tunnel junction elements and a power gating field-effect transistor, allowing for bit-by-bit power gating with a simple structure by connecting the memory cell to a word line, bit lines, and a power supply line, with the power gating transistor controlling power supply to the flip-flop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a PL driver is provided for each of 32 differential pair STT-MRAM cells (grouped as a grain) for power gating, then power supply control is achieved, but the structure becomes complex and the occupied area increases, preventing high integration
Solution Approach 1:
The invention divides the memory cells into smaller grains, with each grain containing only 2 memory cells (1 differential pair) instead of grouping 32 cells together. This segmentation allows for finer-grained power gating control, where each grain has its own PL driver and control transistor, enabling independent power supply control for each differential pair while maintaining simple structures.
2Loss of energy
If a PL driver is provided for each of 32 differential pair STT-MRAM cells (grouped as a grain) for power gating, then power supply control is achieved, but the occupied area increases, preventing high integration
Solution Approach 1:
The invention divides the memory cells into smaller grains, with each grain containing only 2 memory cells (1 differential pair) instead of grouping 32 cells together. This segmentation allows for finer-grained power gating control, where each grain has its own PL driver and control transistor, enabling independent power supply control for each differential pair while maintaining simple structures.
3Area of stationary object
If only a single memory cell is in a single grain for power gating, then the grain size is minimized, but an AND gate for power saving is necessary for each memory cell which utilizes six transistors, making the structure complex and increasing occupied area
Solution Approach 1:
The invention extracts the power gating function from the traditional AND gate implementation and implements it using a dedicated control transistor (PMOS or NMOS) that directly controls the power supply to each differential pair. This extraction simplifies the structure by replacing the complex 6-transistor AND gate with a single control transistor that works in conjunction with the existing PL driver, achieving power gating with minimal additional transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables small bit power gating with a minimal occupied area, reducing access time and improving integration density by using a small number of transistors for power control.
Implementation Method 1
a flip-flop storing data based on resistance values in a pair of magnetic tunnel junction elements
Implementation Method 2
a power gating field-effect transistor including a current path which has one end connected to the power supply line, and which has another end connected to the flip-flop, ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal
Data Source
AI summary
A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.