Dynamic Redundancy Registers for STT-MRAM Write Error Correction
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Solution Overview
Problem
Spin-transfer torque magnetic random access memory (STT-MRAM) devices suffer from high write error rates due to their inherently stochastic write mechanism, leading to unreliable memory operations.
Innovation Solution
The implementation of dynamic redundancy registers, specifically an e1 register and an optional e2 register, which allow for data verification, re-write operations, and data relocation within the memory bank without affecting throughput or random access addressing, ensuring reliable data storage even with high write error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If STT-MRAM devices use spin-polarized electron tunneling to change magnetization orientation for data storage, then non-volatile memory capability is achieved, but write error rate increases due to stochastic write mechanism
Solution Approach 1:
The patent implements a feedback mechanism by reading back written data and comparing it with the original data to detect write errors. When a write error is detected, the system automatically re-writes the data until successful, thereby improving reliability while maintaining non-volatile storage capability
Solution Approach 2:
The patent performs preliminary verification by reading data immediately after writing and comparing it with the source data before considering the write operation complete. This preliminary action detects stochastic write errors and triggers re-write operations, resolving the contradiction between non-volatile capability and write reliability
2Reliability
If dynamic redundancy registers are added to verify and re-write data words, then data reliability improves, but device complexity increases
Solution Approach 1:
The patent nests the e1 and e2 registers within the existing memory bank structure, integrating error verification and re-write functionality into the current architecture rather than adding completely separate systems. This reduces the impact on device complexity while maintaining data integrity
Solution Approach 2:
The dynamic redundancy registers serve multiple functions: storing data words awaiting verification, holding re-write operations, and maintaining address information. This multi-functionality reduces the need for additional separate components, mitigating the increase in device complexity
3Reliability
If verify and re-write operations are performed for failed write operations, then write error rate decreases, but processing time increases
Solution Approach 1:
The patent maintains continuous data flow by piping new data words into the e1 register while verification and re-write operations are performed on previous data. This continuous processing minimizes idle time and reduces the overall impact on processing throughput
Solution Approach 2:
The system performs verification operations immediately after write operations in a pipelined manner, detecting errors early and triggering re-write operations without waiting for complete processing cycles. This preliminary detection and immediate re-action reduces the total time lost to error correction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dynamic redundancy registers enable STT-MRAM devices to maintain data integrity and reliability by verifying and re-writing data words that fail to write correctly, thereby reducing the impact of high write error rates and ensuring consistent memory operations.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Implementation Method 2
The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer.
Data Source
AI summary
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.