STT-MRAM Dynamic Redundancy Registers for Write Error Correction
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Solution Overview
Problem
Spin-transfer torque magnetic random access memory (STT-MRAM) devices suffer from high write error rates due to their inherently stochastic write mechanism, leading to unreliable memory operations.
Innovation Solution
The implementation of dynamic redundancy registers, specifically an e1 register and an optional e2 register, which allow for data verification, re-write attempts, and data relocation within the memory bank, ensuring high write error rate tolerance without compromising throughput or random access addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If STT-MRAM devices use spin-polarized current to switch magnetization, then write speed can be achieved, but write error rate increases due to stochastic mechanism
Solution Approach 1:
The patent introduces a verify operation that is performed immediately after a write operation to check if the data was successfully written. This preliminary verification allows the system to detect write failures before they propagate, enabling corrective actions to be taken while the memory state is still accessible and the write process is fresh in the operation history.
Solution Approach 2:
The patent implements a feedback mechanism where the result of the verify operation is used to determine subsequent actions. If the verify operation detects a write failure, the system automatically triggers a re-write operation. This closed-loop feedback ensures that write errors are detected and corrected, transforming the stochastic write process into a reliable operation through iterative verification and correction.
2Reliability
If verify and re-write operations are implemented to reduce write errors, then reliability improves, but throughput may be compromised
Solution Approach 1:
The patent segments the write operation into distinct phases: the initial write operation, the verify operation, and the conditional re-write operation. This segmentation allows each phase to be optimized independently and enables parallel processing potential, where successful writes can proceed to the next memory operation while failed writes undergo verification and re-write, thus maintaining overall throughput while improving reliability.
Solution Approach 2:
The patent changes the operational parameters dynamically based on verify results. When a write operation succeeds, the system quickly transitions to the next operation with minimal delay. When verification fails, the system adjusts by initiating a re-write operation. This parameter change approach ensures that the overhead of verification and re-write operations is incurred only when necessary, thereby maintaining high throughput for successful operations while ensuring reliability through targeted error correction.
3Reliability
If multiple re-write attempts are made to correct write failures, then write reliability improves, but time consumption increases
Solution Approach 1:
The patent applies partial action by implementing a limited number of re-write attempts rather than infinite retries. The system performs verify operations and re-write operations up to a configured number of attempts, balancing the need for reliability with the cost of time. This partial action approach ensures that write reliability is improved through multiple attempts when necessary, while preventing excessive time consumption by imposing a reasonable limit on re-write operations, thus avoiding indefinite delays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dynamic redundancy registers enable reliable data storage and retrieval in STT-MRAM devices by verifying and re-writing data words, thereby reducing write errors and maintaining memory integrity even with high write error rates.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Implementation Method 2
one of the plates has its magnetization pinned (i.e., a 'reference layer'), meaning that this layer has a higher coercivity than the other layer and requires a larger magnetic field or spin-polarized current to change the orientation of its magnetization
Implementation Method 3
The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer
Data Source
AI summary
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.