STT-MRAM Selection Device with Dual Transistor Architecture
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Solution Overview
Problem
Existing spin-torque transfer (STT) magnetic random access memory (MRAM) technologies require improved structures for reading and writing magnetic bits, as they often use the same conductor and selection transistor for both operations, limiting the range of currents and efficiency.
Innovation Solution
A selection device comprising at least two transistors, arranged in various configurations, is used to selectively couple the magnetic bit to either a write or read architecture, allowing for distinct states to optimize STT-write and read operations, implemented in silicon-on-insulator (SOI) CMOS technology and potentially radiation hardened.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same conductor and selection transistor are used for both reading and writing magnetic bits, then device complexity is reduced, but the range of currents and operational efficiency are limited
Solution Approach 1:
The selection device is segmented into multiple transistors (first transistor and second transistor) that can be independently controlled. This segmentation allows different current paths to be established for read and write operations, enabling optimized current ranges for each operation type while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The selection device employs dynamic control mechanisms where transistors are selectively enabled or disabled based on the operation type. During write operations, specific transistors are enabled to allow higher write currents, while during read operations, different transistor configurations are used to limit current to safe read levels, providing adaptability without increasing structural complexity.
2Productivity
If higher currents are used for STT-write operations, then write efficiency is improved, but series resistance and power consumption increase
Solution Approach 1:
The selection device acts as an intermediary between the current source and the magnetic bit during write operations. By strategically enabling specific transistors in the selection device, the system can deliver high write currents when needed while providing a controlled current path that manages series resistance effects, thus improving write efficiency without excessive energy loss.
3Measurement precision
If the selection device is configured for optimal read operations, then read precision is improved, but write operation performance deteriorates
Solution Approach 1:
The selection device dynamically reconfigures its transistor states depending on the operation type. For read operations, transistors are configured to provide precise current control and accurate resistance measurement. For write operations, the same selection device reconfigures to enable higher current paths that optimize write speed. This dynamic adaptability allows the system to achieve both read precision and write performance without permanent structural compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a wider range of currents for STT-write and read operations, optimizing the processes and reducing series resistance, thereby enhancing the performance of STT-MRAM.
Implementation Method 1
passing a spin-polarized current through the given magnetic bit that is capable of changing the polarity of the given magnetic bit's free layer. In this respect, if the spin-polarized current electrons have to change their spin upon entering the given magnetic bit, those electrons may generate a torque that changes the polarity of the given magnetic bit's free layer
Implementation Method 2
The logic state of MTJ depends on a relative polarity of the free and pinned magnetic layers. For example, if the free and pinned magnetic layers have the same polarity, the MTJ may be storing a logic state '0.' As another example, if the free and pinned magnetic layers have an opposite polarity, the MTJ may be storing a logic state '1.' The MRAM may determine ('read') the logic state of a given magnetic bit by passing a read current through the given magnetic bit and then determining a resistance of the given magnetic bit
Data Source
AI summary
A spin-torque transfer magnetic random access memory (STT-MRAM) that includes a magnetic bit coupled between a first conductor line and a selection device. The selection device includes at least two transistors. The selection device is operative to (a) select the magnetic bit for a spin-torque transfer (STT) write operation when the at least two transistors are in a first state and (b) select the magnetic bit for a read operation when the at least two transistors are in a second state. The selection device may be implemented in silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology, and the transistors may include body ties. The selection device may also be radiation hardened.