STT-MRAM Sensing Technique Using Series Voltage Divider
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing STT-MRAM sensing technologies face challenges in accurately sensing low voltage signals due to random device variations and FET mismatch, which can lead to overlapping resistance distributions and increased read voltages, making it difficult to distinguish logic zero and logic one states without disturbing the memory cell.
Innovation Solution
The system employs a series voltage divider configuration with a sample-and-hold sense amplifier, where a selected memory cell is connected in series with a reference cell during two phases, allowing for a globally generated and controlled read voltage, and offset cancellation techniques to minimize the effects of FET mismatch, ensuring accurate sensing without disturbing the reference cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a relatively large voltage is forced across the cell from BL to SL for writing, then the selected cell's MTJ can be written into a particular state, but the read operation cannot use the same voltage level without disturbing the cell
Solution Approach 1:
The patent segments the sensing operation into two distinct phases: a first sensing phase where the selected memory cell is connected in series with a first reference cell, and a second sensing phase where it is connected in series with a second reference cell. This segmentation allows different reference cells to be used for different sensing operations, enabling accurate differentiation of low resistance states without applying excessive voltage that would disturb the cell.
Solution Approach 2:
The patent changes the parameter being measured from absolute resistance to differential voltage. By measuring the voltage difference between two sensing phases with different reference cells, the system can detect small resistance changes (from 10KΩ to 20KΩ) using low voltages, avoiding the need to apply large voltages that would cause read disturbance.
2Reliability
If the sense voltage is kept low to avoid disturbing the cell, then read reliability is improved, but the ability to distinguish logic zero and logic one states deteriorates due to overlapping resistance distributions
Solution Approach 1:
The patent introduces reference cells as intermediary elements that facilitate the measurement process. By connecting the selected memory cell in series with reference cells having known resistance states (0 or 1), the system creates a voltage divider where the voltage at the tap point provides information about the memory cell's state. This intermediary approach enables accurate state differentiation even with low sensing voltages.
Solution Approach 2:
The patent implements a feedback mechanism where the sense amplifier compares the voltage from the first sensing phase with the voltage from the second sensing phase. Based on this feedback comparison, the system can determine whether the memory cell is in a low resistance or high resistance state, achieving reliable state differentiation without requiring high sensing voltages.
3Ease of manufacture
If FET mismatch and random device variations are present, then manufacturing is simplified, but sensing accuracy deteriorates due to overlapping resistance distributions
Solution Approach 1:
The patent performs preliminary action by pre-characterizing reference cells during manufacturing to determine their resistance states. These reference cells are programmed during fabrication to have known states (0 or 1), and this preliminary characterization is stored and used during operation to compensate for device variations and mismatch, maintaining sensing accuracy despite manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate sensing of low voltage signals while being insensitive to as-manufactured and age-related FET mismatch, providing a simple, power-efficient, and area-efficient solution compatible with advanced node technologies, with improved control over read voltages and reduced sensing errors.
Implementation Method 1
When the cell is in a logic zero (0) or parallel state, its MTJ resistance is lower than when the cell is in a logic one (1) or anti-parallel state. Typical MTJ resistance values would include R0=10 KΩ and R1=20 KΩ.
Implementation Method 2
During a first sensing phase the switching system is configured to open a first series communication path that places the selected memory cell in series with the first reference cell, thereby creating a first series voltage divider.
Data Source
AI summary
Embodiments are directed to a system for sensing a data state of a selected memory cell. The system includes a first reference cell, a sample-and-hold sense amplifier and a switching system. During a first sensing phase the switching system is configured to open a first series communication path that places the selected memory cell in series with the first reference cell, thereby creating a first series voltage divider. During the first sensing phase, the switching system is further configured to open a first branch communication path that taps an input of the sample-and-hold sense amplifier into a first divided voltage between the selected memory cell and the first reference cell.