STT-MRAM State Retention for Low Power Standby

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Solution Overview

Problem

Current electronic devices face significant power consumption issues during standby modes due to the need to maintain state information in volatile memory, which requires continuous power to preserve data, leading to inefficiencies in power usage and time when transitioning in and out of standby states.

Innovation Solution

The integration of spin torque transfer (STT) magnetic random access memory (MRAM) as a non-volatile internal memory within the electronic system, which retains state information using magnetic polarity rather than electrical charge, reducing power consumption and transfer time by allowing power to be completely removed during standby and quickly restored when needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If volatile memory (SRAM/DRAM) is used to store state information, then fast access speed is achieved, but continuous power is required to maintain data, increasing power consumption during standby

Engineering Contradiction:
Improvememory access speedVSAvoidpower consumption during standby
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The memory system is segmented into volatile memory (SRAM/DRAM) for fast access and non-volatile magnetic memory for power-efficient state retention. During standby, only the non-volatile memory remains active, while the volatile memory can be powered down, thus reducing power consumption while maintaining fast access capabilities when needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Non-volatile magnetic memory acts as an intermediary between the volatile memory and external storage. It captures state information from volatile memory during active operation and restores it during wake-up, eliminating the need for continuous power to volatile memory during standby while enabling rapid restoration of state.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If power is completely removed during standby to save energy, then power consumption is minimized, but state information is lost in volatile memory

Engineering Contradiction:
Improvepower leakage during standbyVSAvoidstate information retention
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

Before power is removed during standby, state information is preliminarily transferred from volatile memory to non-volatile magnetic memory. This preliminary action ensures that when power is completely removed, the state information is safely preserved in the non-volatile memory, preventing any loss of information while achieving minimal power consumption.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The state information is copied from volatile memory to non-volatile magnetic memory during the transition to standby mode. This copying mechanism ensures that an identical copy of the state exists in power-independent storage, allowing the volatile memory to be powered down without losing information.

Inventive Principle:
Principle #26Copying

3Use of energy by moving object

If flash memory is used as external non-volatile storage, then power can be removed during standby, but access speed is too slow for immediate resumption of operations

Engineering Contradiction:
Improvepower consumption during standbyVSAvoidwake-up and state restoration speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The non-volatile magnetic memory provides locally optimized properties for state retention with faster access characteristics compared to external flash memory. By placing non-volatile memory closer to the processing units (in the same package or chip), the system achieves both power efficiency during standby and rapid state restoration during wake-up, overcoming the speed limitation of external flash storage.

Inventive Principle:
Principle #3Local quality

4Loss of energy

If state information is transferred to external storage during standby, then power consumption is reduced, but transfer time and energy are increased

Engineering Contradiction:
Improvepower consumption during standbyVSAvoidstate transfer time
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The non-volatile magnetic memory is nested within or integrated with the volatile memory structure, creating a hierarchical memory system. This nesting allows for extremely fast data transfer between the two memory types compared to external storage, as the transfer occurs over short on-chip interconnects rather than through external buses, thereby reducing both transfer time and energy consumption.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution significantly reduces power consumption and transition times by allowing instantaneous restoration of state information, enhancing the 'instant-on' functionality while minimizing power leakage during standby, thus improving battery life and user experience.

Implementation Method 1

retains state information using magnetic polarity rather than electrical charge

Methodology Applied
Scientific EffectMagnetic polarity: Magnetism

Implementation Method 2

spin torque transfer (STT) magnetic random access memory (MRAM)

Methodology Applied
Scientific EffectSpin torque transfer:

Data Source

PatentEP2350768B1Low power electronic system using non-volatile magnetic memory
Publication Date: 2015.05.13 QUALCOMM INC
  • EP2350768B1 patent drawingFigure 1~2
  • EP2350768B1 patent drawingFigure 3~4
  • EP2350768B1 patent drawingFigure 5~6

AI summary

A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit.