STT-MRAM Test Circuit with Parallel Bank Architecture
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Solution Overview
Problem
Semiconductor memory devices, particularly those with resistive memory cells like MRAM, face challenges in detecting failures and enhancing performance due to the need for faster and more integrated memory components, requiring effective testing methods to ensure operational efficiency and reliability.
Innovation Solution
A semiconductor memory device is designed with a memory cell array, a mode register set, and a test circuit that includes a read leveling test operation using a pattern storage circuit, a parallel bit test operation to detect failed cells, and a boundary scan test operation to detect inner connection failures, utilizing spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells with magnetic tunnel junction elements and a transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential testing methods are used for resistive memory cells, then testing can be performed with simple circuitry, but test time is excessive and productivity is reduced
Solution Approach 1:
The memory cell array is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can be tested independently and in parallel. Each bank can undergo read leveling tests, parallel bit tests, or boundary scan tests simultaneously with other banks, significantly reducing total test time while maintaining manageable circuit complexity through modular organization
Solution Approach 2:
The test circuit is designed with multi-functional capability to perform three different types of test operations (read leveling test, parallel bit test, boundary scan test) using the same hardware infrastructure. The mode register set configures the test circuit to execute different test modes, eliminating the need for separate dedicated circuits for each test type and reducing overall device complexity
2Measurement precision
If read leveling test operation is implemented using pattern storage circuit, then timing skew in data output can be detected, but additional circuit components are required
Solution Approach 1:
A pattern storage circuit is pre-configured with specific data patterns (e.g., alternating 0s and 1s) before the read leveling test begins. This preliminary preparation allows the test circuit to directly compare expected patterns with actual read outputs, enabling precise timing skew detection without requiring complex real-time pattern generation circuitry during the test operation
3Reliability
If parallel bit test operation is used to detect failed cells, then test coverage is improved, but test circuit complexity increases
Solution Approach 1:
The parallel bit test functionality is merged with the existing memory bank structure and mode register set configuration. The test circuit utilizes the same wordlines, bitlines, and sense amplifiers used for normal memory operations, combining fail detection capability with existing infrastructure rather than adding completely separate test hardware, thus improving reliability while limiting complexity increase
4Reliability
If boundary scan test operation is implemented, then inner connection failures can be detected, but device complexity increases
Solution Approach 1:
The boundary scan test functionality is implemented using the memory cells themselves as storage elements for test data. The memory banks store test patterns and expected results, and the mode register set controls the test sequence, allowing the device to perform self-diagnosis of internal connections without requiring external test equipment or additional dedicated scan circuitry, thereby detecting connection failures while minimizing complexity increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient detection of failed cells and inner connection issues, improving the reliability and performance of semiconductor memory devices by allowing for parallel testing and reducing test time, thereby enhancing productivity and operational speed.
Implementation Method 1
magneto-resistive random access memory (MRAM) realizes memory function using change of resistance depending on change of polarity of magnetic materials
Implementation Method 2
spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.