STT-RAM MTJ Etching with Encapsulation and Clean-up
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Solution Overview
Problem
Spin-transfer torque (STT) random access memory (RAM) faces challenges in patterning the magnetic stack due to etch-induced damage and redeposition of conductive materials, which degrades performance, especially as dimensions scale below 40 nm, requiring a non-damaging etch process for dense arrays with near vertical sidewalls for electrical isolation.
Innovation Solution
A method involving near normal incidence etching of the magnetic tunnel junction (MTJ) stack, followed by clean-up etches at larger angles to remove redeposited materials, encapsulation layer deposition to preserve the sidewall profile, and subsequent etching while maintaining the encapsulation layer, along with optional use of diamond-like carbon (DLC) hard masks and directional deposition to achieve vertical sidewalls and prevent corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching is used to pattern the magnetic stack, then the structure can be formed, but etch-induced damage degrades the performance of the magnetic tunnel junction
Solution Approach 1:
The patent changes the etching parameters by using low energy ion beam etching (100-500 eV) instead of conventional high energy plasma etching. This parameter change reduces ion-induced damage to the magnetic tunnel junction while still achieving adequate etching rates and profile control
Solution Approach 2:
The patent replaces conventional plasma-based chemical etching with ion beam physical vapor deposition (IB-PVD) etching. This substitution uses physically sputtered ions at low energies to remove material, minimizing chemical reactions and associated damage to the sensitive MTJ stack
2Manufacturing precision
If etching is performed to remove material, then the structure is patterned, but redeposited conductive material condenses on sidewalls and creates electrical shorts
Solution Approach 1:
The patent introduces a temporal dimension to the etching process by performing it in multiple sequential steps with different parameters. The first etch step patterns the structure, while subsequent clean-up etch steps remove redeposited material, effectively adding a time-based separation between pattern formation and contamination removal
Solution Approach 2:
The patent applies preliminary protective actions by depositing encapsulation layers (such as aluminum oxide or silicon nitride) on the sidewalls before the main etching process. These pre-applied protective layers prevent conductive material from condensing on the sidewalls during etching, thereby preventing electrical shorts between adjacent structures
3Productivity
If dimension scaling is performed below 40 nm, then device density increases, but etch-induced damage and redeposition effects become more severe
Solution Approach 1:
The patent changes the energy parameter of the ion beam to very low levels (100-500 eV), which reduces the penetration depth and damage zone in scaled structures. This low energy parameter allows adequate etching of sub-40 nm features while minimizing damage accumulation that would be more severe at smaller dimensions
Solution Approach 2:
The patent segments the etching process into multiple distinct steps: a main patterning etch step followed by separate clean-up etch steps. This segmentation allows each step to be optimized for its specific purpose, with the main step creating the pattern and subsequent steps removing redeposited material, thereby addressing the exacerbated contamination problems in scaled devices
4Reliability
If aggressive etching is used to achieve vertical sidewalls, then electrical isolation between adjacent bits is improved, but damage to the magnetic tunnel junction increases
Solution Approach 1:
The patent applies preliminary protective encapsulation layers on the sidewalls before etching. These pre-deposited layers (aluminum oxide, silicon nitride, or diamond-like carbon) act as protective barriers during the etching process, enabling the use of etching parameters that produce vertical sidewalls for electrical isolation while the protective layer absorbs the ion bombardment damage that would otherwise harm the MTJ
Solution Approach 2:
The patent replaces aggressive plasma chemistry with low energy physical sputtering. This substitution achieves sidewall verticality through controlled physical removal of material at low ion energies, avoiding the chemical reactions and high energy bombardment that cause MTJ damage in conventional aggressive etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes etch-induced damage, maintains near vertical sidewalls, and prevents electrical shorts, enabling scaling down to sub-20 nm dimensions while ensuring the integrity and performance of STT-RAM structures.
Implementation Method 1
Ion beam etching of the stack just past the magnetic tunnel junction (MTJ) with the etching performed at a near normal incidence angle
Implementation Method 2
depositing an encapsulation layer over the cleaned up etched sidewalls
Data Source
AI summary
This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.