STT-RAM MTJ Composite Free Layer for Low Critical Current
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Solution Overview
Problem
Current Magnetic Tunneling Junction (MTJ) elements in Spin-Transfer Torque RAM (STT-RAM) devices face challenges in achieving high dR/R ratios and low critical current densities, which are essential for high-density memory applications, while maintaining the integrity of the tunnel barrier layer and avoiding electrical breakdown.
Innovation Solution
A MTJ structure with a composite free layer configuration of Co40Fe40B20/FeSiO/Co40Fe40B20 and a crystalline MgO tunnel barrier, along with a Ru capping layer, is used to enhance the spin transfer mechanism, reducing the critical current density and maintaining high dR/R ratios, and the layers are fabricated using a process that includes sputtering and thermal annealing to achieve vertical nanopillar profiles suitable for high-density STT-RAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MTJ structure with single ferromagnetic layers is used, then the device structure is simple, but the critical current density is high and dR/R ratio is insufficient
Solution Approach 1:
The free layer is segmented into multiple ferromagnetic layers (first free layer and second free layer) with different magnetization directions, allowing independent optimization of each layer's contribution to TMR ratio and switching characteristics, thereby achieving high dR/R with reduced critical current density
Solution Approach 2:
The MTJ structure employs composite material design with multiple ferromagnetic layers (CoFeB, CoFe) and non-magnetic spacer layers (Ru, Ta) to create a multi-layer free layer structure that enhances spin transfer efficiency and achieves both high dR/R ratio and low critical current density
2Productivity
If high-density memory applications are targeted, then the device area is reduced, but the achievement of high dR/R and low critical current density becomes more difficult
Solution Approach 1:
The free layer is divided into multiple segments with different magnetization orientations, allowing each segment to contribute optimally to the TMR effect while maintaining compact device dimensions suitable for high-density memory applications
Solution Approach 2:
The invention optimizes multiple parameters including layer thicknesses, material compositions, and magnetization directions to achieve high dR/R ratio and low critical current density in miniaturized devices, enabling high-density memory with maintained performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a high dR/R ratio of about 100% with a junction resistance area (RA) of less than 15 ohm-μm² and a critical current density of 2.5×10⁶ A/cm² or less, facilitating magnetization switching without compromising the tunnel barrier, thus enabling enhanced performance in high-density STT-RAM devices.
Implementation Method 1
spin transfer (Spin-RAM) device that achieves low switching current and high dR/R by incorporating a free layer having a FeCoB/FeSiO/FeCoB configuration
Implementation Method 2
The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons
Implementation Method 3
Both MRAM and STT-RAM have a MTJ element based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer
Implementation Method 4
a high λS and high Hc leads to high anisotropy for greater thermal stability
Implementation Method 5
the layers are fabricated using a process that includes sputtering and thermal annealing
Implementation Method 6
the layers are fabricated using a process that includes sputtering and thermal annealing
Data Source
AI summary
A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by a NOX process, a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0, and a Ru capping layer to enhance the spin scattering effect and increase dR/R. Good write margin is achieved by modifying the NOX process to afford a RA less than 10 ohm-μm2 and good read margin is realized with a dR/R of >100% by annealing at 330° C. or higher to form crystalline CoFeB free layers. The NCC thickness is maintained in the 6 to 10 Angstrom range to reduce Rp and avoid Fe(Si) granules from not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A FeSiO layer may be inserted below the Ru layer in the capping layer to prevent the Ru from causing a high damping constant in the upper CoFeB free layer.