STT-MRAM Bypass Determination Unit for Defect Address Handling
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Solution Overview
Problem
Conventional MRAM devices face challenges in handling defects during memory reading and writing, particularly in high-density arrays, as existing methods require additional components and high voltage circuits for defect area addressing, which are uneconomical in terms of die size and power consumption.
Innovation Solution
A spin transfer torque magnetic random access memory (STT-MRAM) device with a bypass determination unit that stores defect area addresses in volatile information storage elements, allowing for comparison with access addresses and diverting access to a spare area when a match is detected, eliminating the need for additional components and power circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to store defect area addresses in fuses or EEPROMs, then defect handling capability is provided, but additional components and high voltage circuits are required which increase die size and power consumption
Solution Approach 1:
The patent merges the defect address storage function with the existing volatile memory array by using column-parallel volatile memory cells to store defect addresses. This eliminates the need for separate fuse or EEPROM components, reducing device complexity while maintaining defect handling capability. The volatile memory cells are integrated within the same array structure, allowing defect addresses to be stored without additional external components.
Solution Approach 2:
The volatile memory cells in the array serve multiple functions: they function as both regular memory storage cells during normal operation and as defect address storage elements when needed. This multi-functionality eliminates the need for dedicated defect storage components, reducing die size and power consumption while providing comprehensive defect handling capability.
2Adaptability or versatility
If additional components and power-providing circuits are formed to handle defects, then defect area addressing is enabled, but die size and power consumption increase
Solution Approach 1:
The volatile memory cells utilize their inherent retention capability to store defect addresses without requiring external power-providing circuits. The cells maintain their stored state during normal operation, eliminating the need for additional power management hardware. This self-service approach reduces power consumption while enabling defect area addressing capability.
3Reliability
If high voltage circuits are added to store defect addresses in EEPROM, then defect address storage is achieved, but die size increases
Solution Approach 1:
The patent combines the defect address storage function with the existing memory array structure by using column-parallel volatile memory cells. This integration eliminates the need for separate EEPROM components and high voltage circuits, reducing die size while maintaining reliable defect address storage capability within the same physical footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces die size and power consumption by eliminating the need for additional components and power-providing circuits, enabling efficient defect handling in MRAM devices without increasing costs or complexity.
Implementation Method 1
volatile information storage element for storing the defect area address
Implementation Method 2
address comparison units having one end to which one bit of an access address is provided and the other end to which one bit stored in the address capacitor is provided
Data Source
AI summary
A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.