STT-MRAM Bitcell With Shared Source Lines for eFlash Replacement

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Solution Overview

Problem

Existing STT-MRAM devices face challenges in scalability below 28-nm technology nodes due to limitations in floating gate/charge trapping technology, necessitating a cost-effective and power-efficient replacement for embedded flash memory applications.

Innovation Solution

The implementation of a spin transfer torque magnetic random access memory (STT-MRAM) device with a parallel source line/bit line (SL//BL) structure, where each bitcell includes a magnetic tunnel junction (MTJ) element coupled in series with an access transistor, and a word line (WL) coupled to the gate of the access transistor, allowing for shared source lines between adjacent columns of STT-MRAM cells, enabling efficient write, erase, and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If floating gate/charge trapping technology is used for eFlash, then eFlash products can be manufactured, but scalability below 28-nm is not achievable

Engineering Contradiction:

ImproveeFlash manufacturingVSAvoidscalability

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent changes the fundamental technology parameter from floating gate/charge trapping to spin transfer torque magnetic random access memory (STT-MRAM), which enables scalability below 28-nm while maintaining eFlash-like functionality. This parameter change allows the memory technology to adapt to advanced technology nodes where traditional eFlash becomes unscalable.

Inventive Principle:

Principle #35Parameter changes

2Area of moving object

If STT-MRAM cell size is reduced, then smaller memory devices are achieved, but read energy and speed may be degraded

Engineering Contradiction:

ImproveSTT-MRAM cell sizeVSAvoidread energy

Core Design Contradiction:

Area of moving objectVSUse of energy by moving object

Solution Approach 1:

The patent merges the source lines of adjacent columns into shared source lines, reducing the total number of source lines from N to N/2. This merging strategy reduces the overall device area and allows for smaller cell sizes while maintaining read performance through optimized bit line and source line architecture that minimizes parasitic resistance and maintains signal integrity.

Inventive Principle:

Principle #5Merging (Combining)

3Area of moving object

If STT-MRAM cell size is reduced, then smaller memory devices are achieved, but write energy may increase

Engineering Contradiction:

ImproveSTT-MRAM cell sizeVSAvoidwrite energy

Core Design Contradiction:

Area of moving objectVSUse of energy by stationary object

Solution Approach 1:

The patent segments the memory array into columns with shared source lines, allowing for optimized current paths during write operations. This segmentation strategy enables better control of write current distribution, reducing the energy required per cell while maintaining the benefit of reduced cell size through the shared architecture.

Inventive Principle:

Principle #1Segmentation

4Area of stationary object

If shared source lines are used between adjacent columns, then device area is reduced, but parasitic resistance may increase

Engineering Contradiction:

Improvedevice areaVSAvoidparasitic resistance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent implements shared source lines in a dimensional arrangement where source lines extend vertically to serve multiple columns, while bit lines extend horizontally. This dimensional change in the layout architecture allows for reduced device area through sharing while managing parasitic resistance through optimized routing and positioning of the shared source lines relative to the bit lines and memory cells.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in smaller cell size, reduced parasitic resistance, improved read/write margins, and efficient sector erase operations, making STT-MRAM devices suitable for advanced technology nodes as a viable eFlash replacement with lower power consumption.

Implementation Method 1

spin transfer torque magnetic random access memory (STT-MRAM) device

Methodology Applied

Scientific EffectSpin transfer torque:

Implementation Method 2

magnetic tunnel junction (MTJ) element

Methodology Applied

Scientific EffectMagnetic tunnel junction effect: Magnetoresistance

Data Source

PatentUS9653137B2STT-MRAM bitcell for embedded flash applications

Publication Date: 2017.05.16 GLOBALFOUNDRIES SINGAPORE PTE LTD

AI summary

A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.