STT-MRAM Cell Size Reduction via Vertical Source Line Placement
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Solution Overview
Problem
Conventional STT-MRAM designs face limitations in reducing the size of MRAM cells due to metal and via spacing rules, which restricts the density of memory arrays despite the potential for significant area savings in each cell.
Innovation Solution
The proposed STT-MRAM structure includes a substrate with a select transistor, dielectric layers, a cylindrical memory stack, and source lines arranged in specific horizontal planes, utilizing nitrogen-doped silicon carbide and ultra-low dielectric constant materials, along with tungsten via plugs and damascened copper layers to optimize the layout and reduce cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If source lines are arranged parallel to bit lines in conventional designs, then electrical connections are maintained, but metal and via spacing rules prevent direct overlap, resulting in larger minimum bit cell size
Solution Approach 1:
The source line is moved from a conventional planar arrangement to a different vertical plane (lower horizontal plane) relative to the landing pad, creating a three-dimensional interconnect structure. This vertical separation allows the source line to bypass the metal and via spacing restrictions that would otherwise prevent direct overlap with the bit line, enabling smaller cell area while maintaining manufacturing compliance.
Solution Approach 2:
The source line is positioned within the vertical space occupied by the dielectric layer structure, nesting it in a lower horizontal plane beneath the landing pad level. This nested arrangement allows the source line to coexist with the landing pad and bit line structure without requiring additional lateral spacing, thus reducing the overall bit cell footprint while maintaining proper electrical connections.
2Quantity of substance
If memory cell area is reduced to increase memory density, then more cells can be packed in the array, but maintaining proper electrical connections and turn-on current becomes difficult
Solution Approach 1:
By moving the source line to a lower horizontal plane, the invention creates a vertical stacking arrangement that reduces lateral spacing requirements. This enables smaller memory cell footprints while maintaining adequate current paths through the vertically separated interconnect structure, thus increasing memory density without compromising turn-on current reliability.
Solution Approach 2:
The dielectric layer structure serves as an intermediary that vertically separates the source line from the landing pad level. This intermediate structure allows the source line to be positioned in a lower horizontal plane, enabling compact cell design while maintaining proper electrical connections and current flow characteristics through the vertically organized interconnect architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a reduction in MRAM cell size to approximately 0.022 µm² and a decrease in pitch size from 240 nm to 140 nm, enhancing memory density and addressing issues related to turn-on current, while maintaining efficient electrical connections.
Implementation Method 1
magnetic elements (MTJ elements) having MTJs utilizing a tunnel magneto resistance (TMR) effect
Implementation Method 2
spin-transfer torque magnetoresistive random access memory (STT-MRAM)
Data Source
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AI summary
A magnetic memory cell (100) includes a substrate (10) having a memory region (MA), a transistor (200) within the memory region, a first dielectric layer (310) disposed on the substrate, a landing pad (MP) in the first dielectric layer, a second dielectric layer (320) covering the first dielectric layer and the landing pad, a cylindrical memory stack (MS) in the second dielectric layer, and a source line (SL) in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region (202) of the transistor. The cylindrical memory stack has a bottom electrode (BE) connected to the landing pad and a top electrode (TE) electrically connected to a bit line (BL). The source line is situated in a second horizontal plane and is connected to a source region (203)of the transistor. The second horizontal plane is lower than the first horizontal plane.