STT-MRAM Cell Area Reduction via Vertical Source Line Sharing
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Solution Overview
Problem
The existing structure of spin-transfer torque magnetoresistive random access memories (STT-MRAM) has a large bit-cell area due to the parallel arrangement of source lines and word lines, making it difficult to reduce the cell area effectively.
Innovation Solution
A semiconductor device with a magnetic tunnel junction storage element is designed, featuring pillar-shaped semiconductor layers, gate insulating films, and contact electrodes, where a single second source line is shared among multiple memory cells, reducing the cell area and allowing for different hierarchies of source and bit lines, and the upper portion of the semiconductor layer can function as either n-type or p-type without forming a diffusion layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source lines are arranged parallel to word lines in a planar transistor structure, then the memory cell can be formed with conventional transistor layout, but the bit-cell area becomes large and cell dimensions increase
Solution Approach 1:
The patent transitions from planar transistor architecture to vertically stacked transistor architecture, where the channel extends in the vertical direction perpendicular to the substrate. This dimensional change allows source and bit lines to be arranged in different hierarchical levels, reducing the planar footprint and bit-cell area while maintaining manufacturability through established vertical fabrication processes.
Solution Approach 2:
The patent segments the transistor structure into distinct vertical layers including fin-shaped semiconductor layers, pillar-shaped semiconductor layers, and multiple gate structures at different levels. This segmentation enables independent optimization of each component and allows source lines to serve multiple cells vertically, reducing the area required per cell.
2Adaptability or versatility
If impurity concentration in silicon pillar is reduced to 10^17 cm^-3 or less, then threshold voltage can be controlled by gate material work function, but it becomes difficult to allow impurity to be present in the silicon pillar
Solution Approach 1:
The patent applies different impurity concentrations to different regions: the fin-shaped semiconductor layer maintains low impurity concentration (≤10^17 cm^-3) for threshold voltage control, while the pillar-shaped semiconductor layer can have higher impurity concentration for better electrical contact. This local differentiation allows simultaneous achievement of precise threshold control and ease of manufacturing.
Solution Approach 2:
The semiconductor structure is segmented into fin-shaped and pillar-shaped regions with different impurity profiles. The fin region serves as the active channel with controlled low impurity, while the pillar region serves as contact region that can accommodate higher impurity levels, making manufacturing more feasible.
3Area of stationary object
If a single source line is shared among multiple memory cells, then cell area is reduced, but the structure becomes more complex with multiple hierarchies of source and bit lines
Solution Approach 1:
The patent resolves the complexity issue by arranging source lines and bit lines in different vertical hierarchies. First source lines connect to lower portions of pillar-shaped layers, while second source lines extend perpendicular to first source lines at different levels. This vertical stratification allows single source lines to serve multiple cells without excessive planar complexity.
Solution Approach 2:
The vertically stacked transistor structure enables single source lines to serve multiple memory cells by tapping into different vertical levels. The same source line infrastructure can serve multiple cells through the vertical dimension, reducing overall cell area while maintaining manageable complexity through standardized vertical interconnects.
Data Source
AI summary
A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.