Stub-Lead Semiconductor Package Layout for Higher Strip Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device packages, particularly low pin count types like SOIC and QFN, face challenges in increasing the number of units per strip and require complex manufacturing processes, leading to reduced yield and higher costs.
Innovation Solution
A novel method involving panel molding and stub leads is employed, where semiconductor dies are mounted on a package substrate with leads extending from two opposite sides, and a continuous mold compound forms a panel. The package is then sawed to create individual units with coplanar leads, eliminating the need for additional lead shaping and increasing the number of units per strip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SOIC packages with gull wing leads are used, then board level reliability is improved, but the spacing needed between devices reduces yield
Solution Approach 1:
The package structure is segmented by providing leads that extend from two opposite sides of the molded package body, rather than all leads extending from one side. This segmentation allows for more compact arrangement of multiple devices on a strip, increasing the number of units per strip while maintaining adequate spacing for reliability.
Solution Approach 2:
The lead arrangement transitions from a conventional single-side extension to a dual-opposite-side extension configuration. This dimensional change in lead orientation enables more efficient use of package substrate space, allowing closer spacing between adjacent devices on the strip while preserving board level reliability through proper lead distribution.
2Productivity
If QFN packages are used to increase units per strip, then area is reduced, but board level reliability decreases
Solution Approach 1:
The package design implements local quality by providing leads at specific locations (two opposite sides) rather than uniformly distributing terminals across the entire package perimeter. This localized lead arrangement at opposite sides provides mechanical strength and reliability similar to SOIC packages while maintaining the compact footprint needed for high-density strip mounting.
3Manufacturing precision
If complex manufacturing processes are used, then package quality is improved, but manufacturing cost increases
Solution Approach 1:
The leads are pre-positioned and pre-formed on the package substrate before the molding process. This preliminary action of having leads ready in their final configuration allows the molding process to simply encapsulate the pre-assembled structure, eliminating the need for complex post-molding lead shaping and reducing manufacturing steps while maintaining package quality.
4Ease of operation
If additional lead shaping steps are performed, then lead functionality is improved, but process complexity increases
Solution Approach 1:
The leads are pre-formed with their final functional shape and configuration before the molding process. This preliminary formation of leads in their operational configuration eliminates the need for subsequent lead shaping steps, reducing process complexity while ensuring proper lead functionality for board mounting and electrical connection.
Data Source
AI summary
In a described example, a semiconductor device package includes: a semiconductor die mounted to a device side surface of a device unit of a package substrate, the device unit having leads extending from a die mount area; electrical connections between bond pads on the semiconductor die and the leads of the device unit; and mold compound covering the semiconductor die, the electrical connections, and portions of the leads, the mold compound forming the body of a semiconductor device package for the semiconductor die having a board side surface, and opposing top side surface, and sides between the board side surface and the top side surface; wherein the leads extend outwards on two opposite sides from the body of the semiconductor device package formed by the mold compound and the leads have a board side surface that is coplanar with the board side surface of the mold compound.


