Stub Minimization in Multi-Die Wirebond Assemblies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microelectronic packages face challenges in reducing signal propagation delays and skew, particularly in multi-chip assemblies, due to varying connection path lengths, which can impact circuit performance and increase complexity and cost in compact designs like smartphones and data servers.
Innovation Solution
The design includes a microelectronic package with a substrate having apertures and terminals configured to reduce stub lengths between chips, allowing for more efficient signal routing with fewer routing layers, thereby minimizing propagation delays and skew, and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional chip packages are used with large package areas, then manufacturing and assembly are easier, but the area occupied on the circuit panel is considerably larger than the chip area, reducing compactness
Solution Approach 1:
Multiple microelectronic elements are stacked vertically within a single package substrate, with lower elements positioned beneath upper elements. This nesting approach allows multiple chips to occupy the same footprint area on the circuit panel, dramatically improving space utilization while maintaining ease of manufacturing through standardized package structures.
Solution Approach 2:
The invention transitions from a two-dimensional layout where chips are placed side-by-side on the circuit panel to a three-dimensional stacked configuration. By utilizing the vertical dimension with multiple bonding layers and through-substrate vias, the package accommodates multiple elements within a compact footprint, reducing the overall area occupied on the circuit panel.
2Adaptability or versatility
If connection paths between terminals and chips are extended to accommodate more I/Os, then more connections are available, but signal propagation delays and skew increase, impacting circuit performance
Solution Approach 1:
The connection path is segmented into multiple independent conductive elements distributed across different bonding layers. Each segment connects to adjacent microelectronic elements, breaking down long propagation paths into shorter segments. This segmentation reduces overall signal propagation delay and skew while accommodating a higher number of I/O connections through the distributed architecture.
Solution Approach 2:
The invention utilizes the vertical dimension by routing conductive elements through the substrate via through-substrate vias and arranging bonding layers at different heights. This three-dimensional routing approach allows multiple signal paths to be stacked vertically, increasing the number of available I/O connections without extending the horizontal connection paths that would increase propagation delay.
3Loss of time
If multiple routing layers are used to reduce propagation delays, then signal performance improves, but device complexity and manufacturing cost increase
Solution Approach 1:
Multiple bonding layers are merged into a single integrated package structure, with conductive elements from different layers working together as a unified connection system. This merging approach reduces the need for separate routing layers, simplifying the overall device complexity while maintaining short propagation paths through the combined multi-layer bonding architecture.
Data Source
AI summary
A microelectronic assembly 5 can include first and second microelectronic packages 10a, 10b mounted to respective first and second opposed surfaces 61, 62 of a circuit panel 60. Each microelectronic package 10a, 10b can include a substrate 20 having first and second apertures 26a, 26b extending between first and second surfaces 21, 22 thereof, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface of the substrate and a plurality of contacts 35 exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, and a plurality of terminals 25a exposed at the second surface in a central region 23 thereof. The apertures 26a, 26b of each substrate 20 can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 of each substrate 20 can be disposed between the first and second axes 29a, 29b of the respective substrate 20.