Stub Minimization in Multi-Die Wirebond Assemblies
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Solution Overview
Problem
Conventional microelectronic packages face challenges in minimizing signal propagation delays and skew, particularly in multi-chip assemblies, where varying path lengths between terminals and chips lead to performance issues such as settling time, ringing, jitter, and intersymbol interference, especially in high-frequency signal switching applications.
Innovation Solution
The configuration of microelectronic packages with terminals arranged in central regions of the substrate, rather than peripheral edges, reduces stub lengths by routing common signals through a single common terminal, and optimizing terminal placement to minimize electrical lengths of connections, thereby reducing propagation delays and skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If terminals are arranged at peripheral edges of the substrate, then ease of connection to circuit panel is improved, but stub length increases causing signal propagation delays and skew
Solution Approach 1:
The patent inverts the conventional terminal arrangement by placing terminals in the central region of the substrate rather than at peripheral edges. This inversion allows signal paths to be routed more efficiently through the substrate, reducing stub lengths and propagation delays while maintaining ease of connection to the circuit panel.
Solution Approach 2:
The patent changes the spatial dimension of terminal placement from the periphery (edges) to the center of the substrate. This dimensional repositioning enables optimization of signal path lengths by routing connections through the central region, thereby reducing electrical length and improving signal integrity.
2Adaptability or versatility
If common signals are routed through multiple separate terminals, then connection flexibility is improved, but electrical length increases causing skew and intersymbol interference
Solution Approach 1:
The patent merges multiple separate terminal connections into a single common terminal for routing common signals. By consolidating the connection point for signals such as clock, command, and address signals, the patent reduces the electrical length and eliminates skew between parallel signal paths, thereby reducing intersymbol interference.
3Reliability
If stub lengths are reduced, then signal integrity is improved, but terminal placement constraints increase
Solution Approach 1:
The patent applies local quality by creating a dedicated central region on the substrate specifically for terminal placement. This localized approach optimizes signal paths for terminals while maintaining standard peripheral connections, thereby reducing stub lengths and improving signal integrity without significantly increasing overall device complexity.
Data Source
AI summary
A microelectronic assembly can include first and second microelectronic packages mounted to respective first and second opposed surfaces of a circuit panel. Each microelectronic package can include a substrate having first and second apertures extending between first and second surfaces thereof, first and second microelectronic elements each having a surface facing the first surface of the substrate and a plurality of contacts at the surface of the respective microelectronic element aligned with at least one of the apertures, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between the contacts of each microelectronic element and the terminals. The apertures of each substrate can have first and second parallel axes extending in directions of the lengths of the respective apertures. The terminals of each microelectronic package can be configured to carry all of the address signals transferred to the respective microelectronic package.