Stud Bump Vertical Interconnects for Dielectric Delamination
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Solution Overview
Problem
The existing semiconductor substrate manufacturing processes are complex and costly due to the need for multiple lithography and plating steps, which increase the risk of failure and result in weak bonding between conductive vias and dielectric layers, leading to delamination and poor electrical connectivity.
Innovation Solution
The use of stud bumps formed by wire bonding, which are integrated into two dielectric layers for vertical electrical connections, reducing the number of processing steps and enhancing bonding strength and resistance to normal and shear forces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple lithography and plating steps are used to form conductive vias, then electrical connectivity is achieved, but the manufacturing process becomes complex and costly with increased risk of failure
Solution Approach 1:
The patent extracts the complex multi-step lithography and plating process and replaces it with a simpler wire bonding process to form stud bumps. This removes the problematic manufacturing steps while maintaining the essential function of creating electrical connections through the dielectric layers.
Solution Approach 2:
The patent replaces the chemical/electrical processes of lithography and plating with a mechanical wire bonding process. The wire bonding method uses mechanical deposition to form conductive material, substituting the complex photochemical and electrochemical processes with a more reliable and simpler mechanical system.
2Strength
If conventional lithography and plating processes are used, then conductive vias are formed, but bonding strength is weak leading to delamination
Solution Approach 1:
The wire bonding process performs preliminary action by forming strong metallurgical bonds between the stud bumps and dielectric layers before subsequent processing steps. This preliminary bonding ensures strong adhesion that prevents delamination during later manufacturing operations and device assembly.
Solution Approach 2:
The patent creates composite structures where the stud bumps consist of conductive material (such as copper or aluminum) bonded to dielectric layers. This composite construction provides both electrical conductivity and strong mechanical bonding, preventing delamination while enabling electrical connections.
3Adaptability or versatility
If semiconductor chip size is increased to accommodate more I/O connections, then functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from planar I/O connections to three-dimensional vertical connections using stud bumps that extend through multiple dielectric layers. This dimensional change allows increased I/O connectivity without proportionally increasing the chip's planar footprint, thereby reducing manufacturing costs while maintaining functionality.
Data Source
AI summary
An electronic device includes a first dielectric layer, a second dielectric layer and at least one first stud bump. The second dielectric layer is disposed on the first dielectric layer. The first stud bump is disposed in the first dielectric layer and the second dielectric layer. The first stud bump includes a bump portion and a stud portion, and the stud portion is disposed on the bump portion.