Stud Bump PCB Assembly for Single-Step Layer Interconnection
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Solution Overview
Problem
Existing circuit board lamination processes require multiple drilling and lamination steps, leading to increased space requirements, stress accumulation, and potential failure points due to via holes and repeated heating/cooling, especially when multiple sub-assemblies are involved.
Innovation Solution
The use of stud bumps to electrically couple conductive layers by aligning and collapsing them during a single lamination step, eliminating the need for drilling and reducing stress by integrating semiconductor dies before lamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple drilling and lamination steps are used to assemble sub-assemblies, then electrical connectivity between conductive layers is achieved, but space requirements increase and stress accumulation occurs
Solution Approach 1:
Semiconductor dies are integrated into sub-assemblies before the lamination process. Stud bumps are formed on bond pads of these pre-integrated dies, allowing electrical connectivity to be established during the single lamination step rather than requiring subsequent drilling and plating operations
Solution Approach 2:
The patent combines multiple operations (die integration, stud bump formation, and lamination) into a single lamination step. This merges the electrical interconnection function with the structural bonding function, eliminating the need for separate drilling and plating steps that would otherwise be required
2Reliability
If multiple drilling and lamination steps are used to assemble sub-assemblies, then electrical connectivity between conductive layers is achieved, but stress accumulation and failure points increase
Solution Approach 1:
Semiconductor dies are integrated into sub-assemblies before lamination, and stud bumps are formed on bond pads prior to stacking. This preliminary preparation allows the lamination process to directly establish electrical connections without requiring subsequent drilling operations that would induce stress and create failure points
Solution Approach 2:
By merging die integration and electrical interconnection into the single lamination step, the patent eliminates multiple stress-inducing operations. The bond material simultaneously provides structural bonding and electrical conductivity paths, reducing cumulative stress accumulation compared to sequential drilling and plating operations
3Reliability
If multiple drilling and lamination steps are used to assemble sub-assemblies, then electrical connectivity between conductive layers is achieved, but equipment needs and alignment errors increase
Solution Approach 1:
Semiconductor dies are integrated and stud bumps are formed on bond pads before the lamination process. This preliminary action ensures that all components are pre-positioned and ready for single-step lamination, reducing the need for complex alignment procedures and specialized equipment required for drilling and plating operations
Solution Approach 2:
The patent merges multiple functions (structural bonding, electrical interconnection, and component integration) into a single lamination step. This consolidation reduces equipment requirements compared to sequential drilling, plating, and bonding operations, while also simplifying the overall manufacturing process and reducing alignment errors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces space requirements, minimizes stress, and enhances electrical connectivity while allowing for high-layer count circuit boards with reduced alignment errors and equipment needs.
Implementation Method 1
Laminating includes softening the bond material and pressing the first stud bump against the first bond pad to collapse the first stud bump. After softening the bond material, the bond material is hardened to bond the first sub-assembly to the second sub-assembly
Implementation Method 2
At least one collapsed stud bump extends at least partially through the first non-conductive layer to electrically couple the first conductive layer to the second conductive layer
Implementation Method 3
The bonding machine breaks or melts the wire, such that the ball (stud bump) remains on the bond pad
Implementation Method 4
the bonding operation to mate the stud bumps to the pads on the circuit board collapses the bumps with a thermo-compression bond often with slight ultrasonic motion to create a stronger joint
Data Source
AI summary
A circuit board having a plurality of conductive layers including a first conductive layer and a second conductive layer is provided. The circuit board includes a plurality of non-conductive layers in-between respective conductive layers of the plurality of conductive layers. The plurality of non-conductive layers include at least a first non-conductive layer disposed between the first conductive layer and the second conductive layer. At least one collapsed stud bump extends at least partially through the first non-conductive layer to electrically couple the first conductive layer to the second conductive layer.