Stud Bump PCB Assembly for Single-Step Layer Interconnects
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Solution Overview
Problem
Existing circuit board lamination processes require multiple sequential lamination steps, leading to stress accumulation, increased space requirements due to drilling operations, and potential failure points from via holes, as well as inefficiencies in bonding materials and vertical interconnects.
Innovation Solution
The use of stud bumps to electrically couple conductive layers by aligning and collapsing them during a single lamination step, eliminating the need for drilling and reducing stress by integrating semiconductor dies before lamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple sequential lamination steps are used to assemble circuit board sub-assemblies, then electrical coupling between sub-assemblies can be achieved, but the process time and number of manufacturing steps increase
Solution Approach 1:
The patent combines the lamination process with the formation of electrical interconnects by collapsing stud bumps during a single lamination step. Multiple functions (bonding sub-assemblies and creating electrical connections) are merged into one operation, eliminating the need for separate via drilling and plating steps.
Solution Approach 2:
Stud bumps are pre-formed on the circuit board before the lamination process. This preliminary action allows the electrical interconnects to be ready in advance, so that during lamination they simply need to be collapsed and connected to corresponding pads, rather than being created during or after the bonding process.
2Reliability
If via holes are drilled and plated to create vertical interconnects, then electrical coupling between layers is achieved, but the device complexity and space requirements increase
Solution Approach 1:
The patent extracts the electrical interconnect formation from the traditional via drilling and plating process. Instead of creating holes through mechanical or laser drilling followed by plating, the invention uses pre-formed stud bumps that are simply collapsed during lamination, removing the complex drilling and plating operations entirely.
Solution Approach 2:
The mechanical drilling and plating system is replaced with a thermal-mechanical collapse process. The stud bumps are collapsed using heat and pressure during lamination, substituting the multi-step mechanical drilling and chemical plating process with a simpler thermal-mechanical operation.
3Strength
If traditional lamination with dielectric bonding material is used, then sub-assemblies are bonded together, but stress accumulation occurs from multiple processing steps
Solution Approach 1:
The patent merges the bonding operation with the interconnect formation operation into a single lamination step. By collapsing stud bumps simultaneously with bonding the sub-assemblies, the number of separate high-stress operations is reduced, minimizing cumulative stress accumulation in the final structure.
4Ease of manufacture
If stud bumps are collapsed during lamination, then electrical coupling is achieved without drilling, but precise alignment between sub-assemblies is required
Solution Approach 1:
Alignment features and stud bump positions are predetermined and pre-formed on the circuit board before lamination. This preliminary positioning ensures that when sub-assemblies are brought together, the stud bumps automatically align with corresponding pads, reducing the alignment precision requirements during the actual lamination process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the number of lamination steps, minimizes space requirements, and enhances mechanical and electrical integrity by creating stable interconnects without drilling and plating, while allowing for high-layer count circuit stacks with precise alignment.
Implementation Method 1
softening the bond material
Implementation Method 2
pressing the first stud bump against the first bond pad to collapse the first stud bump
Implementation Method 3
After softening the bond material, the bond material is hardened to bond the first sub-assembly to the second sub-assembly
Data Source
AI summary
A circuit board having a plurality of conductive layers including a first conductive layer and a second conductive layer is provided. The circuit board includes a plurality of non-conductive layers in-between respective conductive layers of the plurality of conductive layers. The plurality of non-conductive layers include at least a first non-conductive layer disposed between the first conductive layer and the second conductive layer. At least one collapsed stud bump extends at least partially through the first non-conductive layer to electrically couple the first conductive layer to the second conductive layer.