Threshold-Based Write Bypass for STT-RAM Cache Energy Reduction
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Solution Overview
Problem
Non-volatile memory devices like STT-RAM consume significant energy for writes and experience high write latency, which can impact system endurance and performance in hierarchical cache management systems.
Innovation Solution
Implementing a threshold-based write bypass mechanism that determines the number of differing bits between cache lines in the first and second level caches, allowing only the differing bits to be written to the second level cache, and writing the modified cache line directly to the main memory if the number of differing bits exceeds a threshold, thereby reducing write operations to the second level cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write back is performed to STT-RAM operating as intermediary memory device, then data is preserved before writing to main memory, but energy consumption increases and write latency increases
Solution Approach 1:
The patent segments the write operation into two parts: first writing only the modified (dirty) bits to the STT-RAM intermediary memory device, and then writing the entire cache line to main memory. This segmentation reduces the number of bits written to the energy-constrained STT-RAM device, thereby reducing write energy consumption while still preserving data reliability.
Solution Approach 2:
The patent applies partial action by performing a partial write operation where only the dirty bits (not the entire cache line) are written to the STT-RAM intermediary memory device. This partial write reduces the write workload and energy consumption on the STT-RAM device while maintaining data integrity through subsequent full write to main memory.
2Use of energy by moving object
If partial write is performed writing only dirty bits to STT-RAM, then write energy is reduced, but device complexity increases
Solution Approach 1:
The patent employs feedback mechanisms through dirty bit tracking and comparison logic that monitors which bits have been modified in the cache line. This feedback system automatically identifies dirty bits and directs the partial write operation only to those specific bits in the STT-RAM device, managing the increased device complexity through automated bit-level tracking and control.
3Loss of time
If last level cache is bypassed and new data is written directly to main memory, then write latency is reduced, but loss of information increases
Solution Approach 1:
The patent performs preliminary action by writing the modified cache line data to the STT-RAM intermediary memory device before bypassing the last level cache and writing directly to main memory. This preliminary write to STT-RAM preserves the modified data, preventing information loss when bypassing the last level cache, while still achieving reduced write latency through the direct path to main memory.
Data Source
AI summary
Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.