Sub-10nm Fin Formation via Epitaxial Growth
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Solution Overview
Problem
Current methods for forming sub-10 nm node structures, such as FinFETs, face challenges with patterning and lithography processes, leading to inconsistent critical dimensions, line edge roughness, and asymmetric spacer profiles due to limitations in multiple patterning and lithography techniques.
Innovation Solution
A method involving the sequential deposition and removal of dielectric layers and columns on a substrate to form sub-10 nm fins with straight sidewalls, utilizing type III-V semiconductor materials for precise epitaxial growth and selective etching to create a negative space template for type IV semiconductor fin formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple patterning processes (SADP, SAQP) are used to form sub-10 nm structures, then feature density increases, but patterning reliability deteriorates due to small pitch size requirements
Solution Approach 1:
The patent replaces conventional lithography-based patterning (optical/mechanical system) with epitaxial growth (chemical system). By using selective epitaxial growth of III-V semiconductor columns followed by selective removal and replacement with type IV semiconductor fins, the process achieves sub-10 nm patterning without being limited by lithographic resolution, thereby improving patterning reliability while maintaining high feature density
Solution Approach 2:
The patent changes the fundamental patterning parameter from lithographic wavelength limits to epitaxial growth control. By controlling the epitaxial growth conditions (temperature, pressure, precursor flow rates) and using selective etching, the process achieves precise sub-10 nm feature formation that is not constrained by optical diffraction limits, resolving the contradiction between high density and reliability
2Manufacturing precision
If litho-etch-litho-etch (LELE) processes are used, then sub-10 nm features can be formed, but line width roughness increases due to diffraction limits and multiple litho-etch cycles
Solution Approach 1:
The patent substitutes multiple litho-etch cycles with a single epitaxial growth-based patterning approach. The selective epitaxial growth of columns followed by selective removal and fin formation eliminates the need for repeated lithography steps, thereby reducing accumulated line width roughness while maintaining precise sub-10 nm feature control
Solution Approach 2:
The patent uses the dielectric layer pattern as a template (negative space template) to guide epitaxial column growth. The columns are formed by copying the inverse of the dielectric pattern, and subsequent selective removal and fin formation copies this pattern again, achieving precise feature replication without the roughness accumulation from multiple litho-etch cycles
3Ease of manufacture
If conventional spacer etching processes are used, then mask patterns can be formed, but asymmetric spacer profiles and line edge roughness occur
Solution Approach 1:
The patent replaces mechanical spacer etching with selective epitaxial growth. Instead of etching spacers to define patterns, the process grows columns selectively in the spaces between dielectric features. This chemical growth approach produces symmetric, uniform columns with smooth sidewalls, eliminating the asymmetric profiles and line edge roughness inherent in conventional spacer etching
Solution Approach 2:
The selective epitaxial growth process is self-aligning and self-defining. The columns grow automatically in the available spaces between dielectric features, with the growth direction and position determined by the underlying substrate and dielectric pattern. This self-service mechanism produces inherently symmetric profiles without requiring additional alignment or etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reliable formation of sub-10 nm fins with uniform straight sidewalls, improving the consistency and performance of FinFET structures by reducing line width roughness and enhancing pattern transfer accuracy.
Implementation Method 1
utilizing type III-V semiconductor materials for precise epitaxial growth
Implementation Method 2
selective etching to create a negative space template for type IV semiconductor fin formation
Data Source
AI summary
Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.