Sub-12 nm Interconnect Patterning for Defect-Controlled Metallization
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving critical dimensions less than 12 nm with high throughput, low defects, and reduced costs, particularly in the integration of back-end-of-line interconnects, due to limitations in patterning and material deposition processes.
Innovation Solution
A method involving sequential deposition and patterning of dielectric and conductive layers, using a combination of photoresists, hard masks, and etching processes, including dual damascene and single damascene techniques, to form precise openings and conductive lines with reduced dimensions, utilizing materials like titanium oxide and copper, and planarization methods to maintain structural integrity and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning and deposition processes are used, then manufacturing costs and defect rates remain high, but achieving critical dimensions less than 12 nm with high throughput becomes difficult
Solution Approach 1:
The patterning process is divided into multiple sequential steps including first and second photoresist applications, multiple etching stages, and intermediate planarization steps. This segmentation allows each step to be optimized independently for precision while maintaining overall throughput through efficient process sequencing.
Solution Approach 2:
A first photoresist layer is applied and patterned before the actual conductive line formation to create a preliminary pattern structure. This preliminary action establishes a foundation for subsequent processing steps, enabling better control over final critical dimensions while streamlining the overall manufacturing flow.
2Area of moving object
If minimum feature size is reduced to improve integration density, then more components can be integrated, but patterning and material deposition processes become more challenging
Solution Approach 1:
Different photoresist materials and processing conditions are used for different regions and steps of the patterning process. The first and second photoresists have different properties optimized for their specific functions, allowing precise control over local feature formation while managing overall process complexity.
Solution Approach 2:
The patent employs composite material structures including multiple photoresist layers, hard mask layers, and dielectric materials with different properties. This composite approach enables each material to contribute its optimal characteristics to the patterning process, achieving high integration density through controlled feature formation.
3Manufacturing precision
If dual damascene and single damascene techniques are used to form precise openings, then conductive lines with reduced dimensions can be achieved, but the number of processing steps increases
Solution Approach 1:
The patent employs dynamic process selection where dual damascene techniques are used in regions requiring high precision opening formation, while single damascene techniques are applied where simpler structures suffice. This dynamic approach optimizes the balance between opening precision and processing step complexity across different device regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of conductive lines with critical dimensions below 12 nm, improving integration density, reducing defects, and lowering manufacturing costs, while avoiding irregular shapes and defects like bird's beak formations, thus enhancing the overall semiconductor device performance.
Implementation Method 1
patterning the various material layers using lithography to form circuit components and elements thereon
Implementation Method 2
depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material
Data Source
AI summary
A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.