Sub-Bank Memory Layout for Burst Error Isolation
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Solution Overview
Problem
Existing memory devices face challenges in managing burst errors due to sub-word line driver failures, leading to increased error bits and inefficiencies in error correction, which can induce system errors and reduce processing speed and data transmission efficiency.
Innovation Solution
The memory device distributes error bits generated by burst errors across multiple sub-banks within bank groups, using control signals to selectively store and read data chunks in specific sub-banks, reducing the number of error bits per chunk and enabling effective error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are enhanced with more parity bits to detect and correct more errors, then error correction capability is improved, but device complexity and processing speed deteriorate
Solution Approach 1:
The patent divides the data storage structure into multiple sub-banks within bank groups, where each sub-bank stores a portion of the data chunk. This segmentation isolates errors to specific sub-banks, reducing the impact on overall error correction requirements and allowing for more efficient parity bit allocation.
Solution Approach 2:
The patent implements local error distribution by storing data chunks across multiple sub-banks with different error correction characteristics. Each sub-bank can be optimized for local error correction needs, allowing the system to maintain high reliability without uniformly increasing complexity across the entire device.
2Reliability
If more parity bits are allocated for error correction, then error detection and correction accuracy is improved, but data transmission efficiency deteriorates
Solution Approach 1:
By segmenting data into multiple sub-banks, the patent enables selective error correction only where needed. This reduces the total number of parity bits required compared to a uniform approach, thereby maintaining higher data transmission efficiency while preserving accurate error correction capability.
Solution Approach 2:
The patent applies error correction selectively to sub-banks that actually contain errors rather than applying correction mechanisms to all data uniformly. This partial action approach reduces overhead and maintains transmission efficiency while ensuring reliable error correction where it matters most.
3Ease of operation
If data is stored in a single sub-bank for simplicity, then device operation is simplified, but burst error impact increases
Solution Approach 1:
The patent segments data storage across multiple sub-banks within bank groups, which simplifies the handling of burst errors. When a burst error occurs in one sub-bank, the error is isolated and does not affect other sub-banks, making the system more resilient to harmful factors while maintaining operational simplicity through automated distribution.
Solution Approach 2:
The peripheral circuit acts as an intermediary that automatically distributes data chunks to appropriate sub-banks based on address signals. This intermediary mechanism handles the complexity of error distribution transparently, presenting a simplified interface to external devices while protecting against burst errors through the underlying multi-sub-bank structure.
Data Source
AI summary
Various embodiments of the present disclosure relate to a memory device, and the memory device may comprise a plurality of bank groups, each bank group including a plurality of banks, each bank including two sub-banks, each sub-bank including a plurality of memory cells, and a peripheral circuit configured to receive a control signal and a data chunk from an external device, and store the data chunk to be distributed in at least two or more sub-banks selected from among sub-banks included in the plurality of bank groups.