Sub-Bank Refresh Scheduling to Reduce DRAM I/O Stalls
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Solution Overview
Problem
The increasing ratio of refresh operations to overall operating time in volatile memory devices, such as DRAM, limits input/output performance due to the need for frequent charge recharging in memory cells.
Innovation Solution
A memory device and host device system that includes a command issuance circuit, debit counters, and a refresh scheduling circuit to manage and skip regular refresh operations by implementing hidden refresh operations for sub-banks, allowing for more efficient use of memory cell rows and reducing the need for frequent regular refresh commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If regular refresh operations are performed at every refresh period, then data integrity is maintained, but input/output performance is limited due to frequent refresh commands
Solution Approach 1:
The memory bank is divided into multiple sub-banks, and the refresh operation is segmented into a first refresh operation for a first sub-bank and a second refresh operation for a second sub-bank. This segmentation allows the memory device to perform refresh operations on different sub-banks at different times, enabling I/O operations to proceed on sub-banks that are not currently being refreshed, thereby maintaining data integrity while improving input/output performance.
2Reliability
If refresh operations are performed frequently to maintain data integrity, then charge leakage is compensated, but the time available for I/O operations is reduced
Solution Approach 1:
The memory device performs the first refresh operation on the first sub-bank before the second refresh operation on the second sub-bank. This preliminary action on the first sub-bank allows subsequent I/O operations to be performed on the first sub-bank while the second sub-bank is being refreshed, effectively preparing one sub-bank for I/O operations in advance and reducing the time loss for I/O operations while maintaining charge integrity.
3Reliability
If the memory device performs refresh operations on the entire memory bank, then all memory cells are refreshed, but the minimum activation period limits the speed of subsequent operations
Solution Approach 1:
The memory bank is segmented into multiple sub-banks that can be refreshed independently. The first refresh operation refreshes only the first sub-bank, and the second refresh operation refreshes only the second sub-bank. This segmentation allows subsequent operations to be performed on sub-banks that have already been refreshed, avoiding the need to wait for the entire memory bank to complete a full refresh cycle, thereby improving operation speed while ensuring all memory cells are eventually refreshed.
Data Source
AI summary
There is provided a host device communicating with a memory device including a first memory bank. The host device includes a command issuance circuit configured to issue a regular refresh command for a first memory bank of a memory device at every regular refresh period, a first debit counter configured to manage a first debit count for a first sub-bank in the first memory bank, a second debit counter configured to manage a second debit count for a second sub-bank in the first memory bank, and a refresh scheduling circuit configured to determine whether to skip issuing the regular refresh command of the command issuance circuit based on the first debit count and the second debit count.