Sub-Binary DAC Self-Calibration for Reference Drop Linearity
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Solution Overview
Problem
High-resolution Digital to Analog Converters (DACs) face challenges in achieving accurate linearity due to code-dependent voltage drops across routing resistances, which are not effectively calibrated, impacting the Integral Non-Linearity (INL) of sub-binary DACs.
Innovation Solution
The implementation of a self-calibration method for sub-binary DACs, where each leg of the R-BR resistor ladder is individually adjusted, and thermometric weightages are measured and corrected to reduce non-linearity, using a segmented architecture with split voltage reference lines to minimize code-dependent voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sub-binary DAC structure is used to generate finer-resolution levels with redundant bits, then the resolution is improved, but the linearity is degraded due to inaccuracies in analog measurements of bit weightages
Solution Approach 1:
The patent segments the DAC into thermometric bits and sub-binary bits, with separate calibration procedures for each segment. The thermometric portion is calibrated first, then the sub-binary portion is calibrated independently, allowing high-resolution output while maintaining linearity through divided calibration zones
Solution Approach 2:
The patent performs preliminary calibration of the thermometric bits before calibrating the sub-binary bits. This sequential preliminary action ensures that the foundation (thermometric portion) is accurately established before adding the finer resolution layers (sub-binary bits), preventing error propagation
2Manufacturing precision
If highly accurate analog trimming procedures are implemented to achieve high accuracy DAC output, then the linearity is improved, but the device complexity and cost increase
Solution Approach 1:
The patent implements self-calibration where the DAC uses its own output to calibrate itself through an on-chip ADC. The system automatically measures its own bit weightages and adjusts calibration values without external intervention, eliminating complex external trimming equipment and procedures
Solution Approach 2:
The patent introduces feedback loops where the DAC output is fed back through an on-chip ADC to measure actual bit weightages. These measurements are used to generate calibration values that are applied back to the DAC, creating a closed-loop system that automatically corrects linearity errors
3Device complexity
If code-dependent voltage drops across routing resistances are not calibrated, then the device complexity is reduced, but the Integral Non-Linearity (INL) deteriorates
Solution Approach 1:
The patent introduces dummy resistors as intermediaries that match the routing resistances in the signal path. These dummy resistors carry calibration currents to measure and compensate for voltage drops in the actual signal paths, indirectly correcting the INL error without requiring direct modification of the signal routing
Solution Approach 2:
The patent changes the calibration approach from direct voltage measurement to current-based measurement through dummy resistors. By measuring calibration currents and calculating equivalent voltage drops, the system compensates for parameter variations in routing resistances without directly measuring or modifying the voltage drops themselves
Data Source
AI summary
A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.