Sub-block Erase Operations in Memory Sub-systems
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Solution Overview
Problem
Conventional memory devices perform erase operations on entire data blocks without support for smaller granularity, leading to increased latency and inefficiency, particularly in multi-dimensional memory devices like 3D NAND, where improved erase operation performance is crucial for advanced architectures.
Innovation Solution
The implementation of sub-block erase operations in a memory sub-system, where select gate devices control the conduction of signals through pillars, allowing for selective erase operations on specific sub-blocks while inhibiting others by gradually reducing the gate voltage to zero volts, thereby minimizing disturbances and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operations are performed on entire data blocks, then complete data erasure is achieved, but latency increases and efficiency decreases
Solution Approach 1:
The data block is divided into multiple sub-blocks, allowing the erase operation to be performed selectively on only the necessary sub-blocks rather than the entire block. This segmentation enables partial erase operations that reduce latency and improve efficiency by processing only the required portions of the data block.
Solution Approach 2:
The patent implements partial erase action by enabling erase operations on selected sub-blocks within a data block without requiring the entire block to be erased. This partial action approach reduces unnecessary processing time and improves overall erase operation efficiency.
2Loss of energy
If gate voltage is gradually reduced to zero volts for unselected sub-blocks, then disturbances are minimized and power consumption is reduced, but additional control complexity is introduced
Solution Approach 1:
Different gate voltages are applied to different sub-blocks based on their selection status. Selected sub-blocks receive the erase voltage while unselected sub-blocks have their gate voltage gradually reduced to zero. This local differentiation minimizes disturbances and power consumption in unselected areas while maintaining erase effectiveness in selected areas.
Solution Approach 2:
The gate voltage for unselected sub-blocks is dynamically adjusted by gradually reducing it to zero volts during the erase operation. This dynamic voltage control prevents disturbances and reduces power consumption adaptively based on the operational requirements of each sub-block.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the granularity and efficiency of erase operations, reducing latency and power consumption by enabling selective erase operations on specific sub-blocks, thus improving overall memory device performance.
Implementation Method 1
select gate devices control the conduction of signals through pillars, allowing for selective erase operations on specific sub-blocks while inhibiting others by gradually reducing the gate voltage to zero volts
Data Source
AI summary
A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.