Sub-block Erase for 3D NAND Memory Arrays
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Solution Overview
Problem
High-density 3D NAND memories face inefficiencies in erase operations due to large block sizes, which hinder performance when only small units of data need to be changed, as the number of layers increases, leading to slower timing specifications for block erase operations.
Innovation Solution
The method involves dividing a set of word lines shared by NAND strings into subsets, allowing for sub-block erase operations where only some memory cells are erased, while inhibiting tunneling in others, using specific biasing arrangements and voltage applications to enable faster and more flexible erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If block erase operations are used in high-density 3D NAND memories, then storage capacity is increased, but erase operation time increases
Solution Approach 1:
The patent divides a block of memory cells into multiple sub-blocks, each with its own set of word lines. This segmentation allows independent erase operations on individual sub-blocks, enabling selective erasure of only the necessary portion of memory cells while leaving other sub-blocks intact, thereby reducing overall erase operation time in high-density 3D NAND memories.
Solution Approach 2:
The patent enables partial erase operations where only specific sub-blocks within a block are erased based on actual data modification needs. This partial action approach avoids the excessive erasure of entire blocks when only small portions of data need to be changed, directly addressing the time loss issue while maintaining the high storage capacity of 3D NAND structures.
2Quantity of substance
If the number of layers in 3D NAND stacks is increased, then storage density is improved, but block size increases leading to slower erase operations
Solution Approach 1:
By segmenting the block into multiple sub-blocks along the vertical stack direction, the patent enables independent control and erasure of individual sub-blocks. This segmentation strategy allows the memory system to maintain high storage density through increased layer count while improving erase operation speed by processing only the necessary sub-blocks rather than entire large blocks.
Solution Approach 2:
The patent applies different voltage conditions to different sub-blocks within the same block, enabling localized erase operations. This local quality approach allows high-density stacks to be erased selectively in specific regions rather than uniformly across the entire block, thereby maintaining storage density while enhancing erase operation speed through targeted processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster timing specifications for sub-block erase operations compared to block erase operations, enhancing the performance of 3D NAND memories by allowing for more efficient and convenient erase of smaller units of data.
Implementation Method 1
allowing for sub-block erase operations where only some memory cells are erased, while inhibiting tunneling in others
Data Source
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AI summary
A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.