Sub-Block Non-Volatile Memory Programming With GIDL Inhibition
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in efficiently programming and erasing non-volatile memory cells due to the limitations of traditional block-based operations, which can lead to interference and reduced endurance of memory cells.
Innovation Solution
The implementation of non-volatile memory cells divided into sub-blocks, where each sub-block can be independently controlled through Gate Induced Drain Leakage (GIDL) generation transistors, allowing separate programming and erasing without affecting unselected sub-blocks, and the use of a control circuit to manage these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional block-based programming and erasing operations are used, then memory operations can be performed, but interference occurs between unselected memory cells and programming efficiency is reduced
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block, second sub-block, etc.), each with independent control capabilities. This segmentation allows selective programming and erasing of specific sub-blocks without affecting others, thereby reducing interference to unselected cells and improving programming efficiency.
Solution Approach 2:
Different sub-blocks are assigned different control signals and voltage levels locally. The control circuit applies specific voltages to word lines and bit lines of selected sub-blocks while maintaining different voltage states for unselected sub-blocks, enabling localized operations that minimize interference.
2Reliability
If traditional block-based operations are used, then memory cells can be programmed and erased, but memory cell endurance is reduced due to unnecessary operations
Solution Approach 1:
By dividing the block into independently controllable sub-blocks, the system can perform operations only on the specific sub-blocks that need modification. This prevents unnecessary programming and erasing cycles on other memory cells, thereby improving endurance while maintaining operation efficiency.
Solution Approach 2:
Instead of performing full block operations, the system applies partial actions by targeting only the specific sub-blocks that require programming or erasing. This reduces the total number of operations on memory cells, improving endurance without sacrificing the efficiency of necessary operations.
3Productivity
If sub-block independent control is implemented, then programming and erasing efficiency is improved, but device complexity increases
Solution Approach 1:
The control circuit is designed with segmented control capabilities, where each sub-block has dedicated control lines and voltage generation circuits. While this increases device complexity, it enables independent programming and erasing of sub-blocks, significantly improving programming and erasing efficiency.
Solution Approach 2:
The patent introduces an additional control dimension by adding sub-block selection signals to the traditional word line and bit line control structure. This dimensional expansion allows precise addressing of individual sub-blocks, improving efficiency despite the increased control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of programming and erasing processes, increases memory cell endurance, and improves overall memory operation efficiency by minimizing unnecessary operations on individual cells.
Implementation Method 1
Each sub-block includes multiple source side Gate Induced Drain Leakage ('GIDL') generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same block so that sub-blocks can be separately and independently erased
Data Source
AI summary
A non-volatile memory includes non-volatile memory cells divided into blocks, bit lines connected to the blocks, and a source line connected to the blocks. Each block includes multiple sub-blocks. Each sub-block includes multiple source side Gate Induced Drain Leakage (“GIDL”) generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same sub-block so that sub-blocks can be separately and independently erased and/or GIDL can be used to inhibit unselected sub-blocks from bring disturbed during programming.