Sub-block Segmentation in 3D NAND via Dual Buried Source Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As NAND flash memory technology advances, increasing string lengths and word line layers lead to larger memory block sizes, making garbage collection inconvenient and reducing memory block yields due to increased bad blocks, while existing solutions fail to efficiently manage sub-block selection and erase operations in three-dimensional non-volatile memory systems.
Innovation Solution
The use of dual buried source lines within a physical memory block allows for individual selection and unselection of sub-blocks in both horizontal and vertical directions, enabling improved block yields and efficient garbage collection by allowing independent biasing of buried source lines during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If NAND flash memory structures increase string lengths and word line layers to scale down process geometries, then cost per bit is reduced, but memory block size increases making garbage collection inconvenient and reducing memory block yields
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be independently selected and erased. This segmentation allows garbage collection to operate on smaller sub-block units rather than the entire memory block, improving efficiency while maintaining the scaled-down process geometry benefits
Solution Approach 2:
The patent implements dynamic sub-block selection capability where different sub-blocks can be independently activated or deactivated based on operation needs. This dynamic control enables flexible garbage collection strategies, allowing the system to target only the necessary sub-blocks for erasure rather than processing the entire memory block
2Ease of manufacture
If NAND flash memory structures increase string lengths and word line layers to scale down process geometries, then cost per bit is reduced, but memory block yields decrease due to increased bad blocks
Solution Approach 1:
By segmenting the memory block into independent sub-blocks with separate selection and erasure capabilities, the patent isolates potential bad blocks to specific sub-blocks. This prevents a single bad block from rendering the entire memory block unusable, thereby improving yields while maintaining scaled process geometries
Solution Approach 2:
The dynamic sub-block selection mechanism allows the system to adaptively activate only healthy sub-blocks for operations. When bad blocks are detected, the corresponding sub-blocks can be selectively deactivated, ensuring that memory block yields are maintained despite the presence of defective regions
3Quantity of substance
If memory block size increases due to larger string lengths and word line layers, then more memory capacity is achieved, but garbage collection becomes inconvenient
Solution Approach 1:
The large memory block is segmented into smaller sub-blocks that can be independently managed. This allows garbage collection to operate on a finer granularity level, making it more convenient to target and erase only the specific sub-blocks that need cleaning rather than processing the entire large memory block
Solution Approach 2:
Instead of performing garbage collection on the entire memory block, the patent enables partial action by allowing selective erasure of only the necessary sub-blocks. This partial approach maintains ease of operation while preserving the total memory capacity provided by the larger block structure
Data Source
AI summary
Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.