Sub-block Stack Structures for 3D Memory Erase Control
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Solution Overview
Problem
In three-dimensional semiconductor devices, increasing the number of stacked memory cells to enhance capacity leads to larger memory blocks, which complicates erase operations, reducing efficiency and reliability.
Innovation Solution
The semiconductor device incorporates sub-block stack structures with source layers and memory block stack structures, allowing for finer control of cell strings in sub-block units, improving operational efficiency and reliability by segmenting memory blocks into smaller sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased to enhance capacity, then the storage capacity is improved, but the memory block size is increased leading to degraded erase operation efficiency and reliability
Solution Approach 1:
The patent divides a memory block into multiple sub-blocks, where each sub-block contains a portion of the stacked memory cells. This segmentation allows erase operations to be performed on individual sub-blocks rather than the entire memory block, thereby maintaining high storage capacity while improving erase operation efficiency and reliability through finer-grained control.
2Quantity of substance
If the number of stacked memory cells is increased to enhance capacity, then the storage capacity is improved, but the memory block size is increased leading to degraded erase operation efficiency
Solution Approach 1:
The memory block is segmented into multiple sub-blocks, enabling selective erase operations on only the necessary portions of memory. This reduces the time and resources required for erase operations compared to erasing the entire memory block, thereby improving erase operation efficiency while maintaining high storage capacity.
3Productivity
If memory blocks are segmented into sub-blocks for finer control, then erase operation efficiency is improved, but the device structure becomes more complex
Solution Approach 1:
The patent implements segmentation by dividing the memory block into sub-blocks with associated control logic. While this increases structural complexity compared to a monolithic memory block, the segmentation enables efficient selective erase operations and improves overall system performance through finer-grained control of memory operations.
Solution Approach 2:
The patent employs three-dimensional stacked memory cells arranged in multiple layers. This vertical stacking approach increases storage capacity without proportionally increasing the footprint area, and when combined with sub-block segmentation, allows for efficient control of large-capacity memory structures through hierarchical organization.
Data Source
AI summary
A semiconductor device includes sub-block stack structures respectively including source layers, where the sub-block stack structures are disposed to be spaced apart from each other along a first direction, a memory block stack structure including word lines stacked over the sub-block stack structures, the word lines being coupled to memory cells, the memory block stack structure extending along the first direction to overlap the sub-block stack structures, and channel layers respectively coupled to the source layers by penetrating the memory block stack structure.