Dynamic Sub-Computation Unit Activation for Power Efficiency
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Solution Overview
Problem
Computation processing apparatuses with SIMD instructions face inefficiencies in processing performance when the number of parallel data pieces is small, leading to unnecessary power consumption due to operational units being active regardless of data load.
Innovation Solution
A computation processing apparatus that includes a processor capable of decoding instructions and operating as multiple sub-computation units based on data bit width, with an observation unit to identify inactive units, allowing for parallelization and efficient instruction execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SIMD computation units operate in parallel regardless of data load, then computation performance is improved, but power consumption increases due to useless operation
Solution Approach 1:
The computation processing apparatus dynamically adjusts the number of active sub-computation units based on the actual computation workload. The control unit determines how many SIMD computation units should be active according to the number of parallel data pieces requiring computation, thereby optimizing the balance between computation performance and power consumption.
Solution Approach 2:
The system changes the operational parameter of the computation units by adjusting the number of active SIMD lanes based on the data bit width and computation requirements. When fewer parallel data pieces are processed, fewer computation units are activated, changing the system's operational state to match the workload.
2Productivity
If the number of SIMD computation units is increased, then processing capacity is improved, but power consumption increases when data load is small
Solution Approach 1:
The system performs partial action by activating only the necessary number of SIMD computation units required for the current computation task. Instead of always running all computation units, the control unit enables only the subset needed for the current data load, avoiding excessive power consumption while maintaining sufficient processing capacity.
Solution Approach 2:
The apparatus transitions from a static configuration where all computation units are always active to a dynamic configuration where the number of active units varies with the computation workload. This dynamic adjustment eliminates useless power consumption while preserving the ability to scale up processing capacity when needed.
3Productivity
If all computation units are activated, then instruction processing throughput is improved, but energy efficiency deteriorates when not all units are needed
Solution Approach 1:
The system changes the operational parameter from a fixed state where all computation units are always active to a variable state where the number of active units is adjusted according to the data bit width and computation requirements. This parameter change optimizes the ratio of instruction processing throughput to energy consumption.
Solution Approach 2:
The control unit implements dynamic control over the activation state of computation units, adjusting the system's operational characteristics in real-time based on the actual computation needs. This dynamic approach maintains high instruction processing throughput when necessary while improving energy efficiency when full capacity is not required.
Data Source
AI summary
A computation processing apparatus includes: a memory; and a processor coupled to the memory and configured to: decode instructions; execute the instructions which is decoded and operate as a plurality of sub-computation processing apparatuses in accordance with a bit width of data to be computed; and observe an operation state of the computation processing apparatus, wherein, when observing that a subset of the plurality of sub-computation processing apparatuses does not execute an instruction or instructions, the processor parallelizes the instructions and outputs the parallelized instructions.


