Sub-Decoder Circuit Layout and Substrate Potential Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In flash memory devices, the miniaturization of memory cells leads to challenges in maintaining stable operation and reducing parasitic MOS leakage current, which increases power consumption and deteriorates dielectric breakdown characteristics, especially when high voltages are applied.
Innovation Solution
A nonvolatile semiconductor memory device with a sub-decoder circuit that includes transistors of the same conductivity type, where the substrate potential is set separately from the source potential, reducing parasitic MOS leakage and allowing for miniaturization without compromising dielectric breakdown characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase integration density, then storage capacity is improved, but parasitic MOS leakage current increases causing power consumption to worsen
Solution Approach 1:
The substrate potential control is segmented from source potential control, with independent control circuits for each. This allows separate optimization of substrate potential to suppress parasitic MOS leakage while maintaining source potential for normal operation, thereby reducing power consumption without sacrificing storage capacity.
Solution Approach 2:
The patent changes the potential parameter by applying a lowered substrate potential (different from source potential) to the well region. This parameter change suppresses parasitic MOS leakage current in miniaturized devices, reducing power consumption while maintaining the storage capacity benefits of miniaturization.
2Quantity of substance
If memory cells are miniaturized to increase integration density, then storage capacity is improved, but dielectric breakdown characteristics deteriorate under high voltage
Solution Approach 1:
The independent substrate potential control segments the electrical environment, allowing the substrate to be held at a different potential than the source. This reduces electric field stress on dielectric layers in miniaturized cells, preventing breakdown while maintaining high storage capacity.
Solution Approach 2:
The substrate potential is lowered beforehand to cushion against high voltage stress before dielectric breakdown can occur. This protective measure is applied continuously to the well region, preventing reliability degradation in miniaturized memory cells that must operate under high voltage conditions.
3Area of stationary object
If sub-decoder elements are miniaturized to reduce layout area, then integration density is improved, but parasitic MOS leakage current increases
Solution Approach 1:
The substrate potential control is segmented independently from source potential control in the sub-decoder circuit. This allows miniaturization of the layout while the independent substrate potential suppression counteracts the increased parasitic MOS leakage from closer spacing, maintaining low power consumption in the compact design.
4Extent of automation
If high voltage is applied for writing operations to achieve data storage, then writing capability is improved, but parasitic MOS leakage current increases causing power consumption to worsen
Solution Approach 1:
The independent substrate potential control segments the voltage management, allowing high writing voltages to be applied to word lines while the substrate potential is independently lowered to suppress parasitic MOS leakage. This enables full writing capability while reducing the power consumption penalty from leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the miniaturization of sub-decoder elements while maintaining stable operation and reducing parasitic MOS leakage, thus improving power efficiency and preventing dielectric breakdown, even under high voltage conditions.
Implementation Method 1
The well region has a potential set separately from the source potentials, by a well potential setting circuit. This reduces parasitic MOS leakage current by utilizing the back-gate effect where the well potential controls the threshold voltage of parasitic MOS transistors formed at the isolation regions.
Data Source
AI summary
A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.