Sub-Fin Wide Channel Diode for High-Current Low-Capacitance ESD
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Solution Overview
Problem
Existing diode structures for integrated circuits face challenges in achieving high current density while minimizing parasitic capacitance, particularly in electrostatic discharge (ESD) protection applications, as they often rely on substrate-based current paths or nanoribbon formations that reduce efficiency.
Innovation Solution
The diode structure incorporates a sub-fin region as the primary current conduction path, with wider nanoribbons and sub-fins compared to adjacent transistors, forming PN junctions and utilizing semiconductor material between nanoribbons to enhance current conduction and reduce turn-on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional substrate-based diode structures are used, then parasitic capacitance is reduced, but current density and current carrying capability are insufficient
Solution Approach 1:
The patent transitions from traditional planar substrate-based diode structures to a vertical FinFET-based diode structure. The FinFET channel extends vertically from the substrate surface, creating a three-dimensional current conduction path that increases current carrying capability while maintaining low parasitic capacitance. The vertical fin structure provides additional current conduction area without increasing lateral footprint, thereby resolving the contradiction between ESD protection capability and current density.
Solution Approach 2:
The diode structure is segmented into distinct doped regions within the FinFET channel: a first doped region (anode), a second doped region (cathode), and an intrinsic region between them. This segmentation creates multiple PN junctions along the vertical fin structure, enabling high current density through the stacked configuration while maintaining electrical isolation and low parasitic capacitance to the substrate.
2Productivity
If wider channel regions are used to increase current conduction, then current density improves, but parasitic capacitance increases
Solution Approach 1:
Instead of increasing lateral channel width, the patent utilizes the vertical dimension of the FinFET structure. The channel width in the lateral plane is kept narrow to minimize parasitic capacitance, while the fin height (vertical dimension) is increased to provide sufficient current conduction area. This dimensional transformation allows high current density without increasing parasitic capacitance.
Solution Approach 2:
The diode structure employs a composite doped configuration within the FinFET channel, combining n-type and p-type doped regions in a vertical stack. This composite structure creates multiple PN junctions that enable high current conduction through the vertical fin while the narrow lateral dimensions maintain low parasitic capacitance to surrounding structures.
3Device complexity
If nanoribbon formations are used, then device integration is improved, but current conduction efficiency is reduced
Solution Approach 1:
Instead of using narrow nanoribbon structures that limit current conduction, the patent inverts the approach by utilizing wider FinFET channel structures. The FinFET channel provides a broader current conduction path while maintaining vertical integration. The inversion from narrow nanoribbon to wider fin structure improves current conduction efficiency while still achieving high device integration through the vertical architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high current density and low parasitic capacitance, making the diodes suitable for ESD protection without relying on substrate-based paths, thereby improving efficiency and current carrying capability.
Implementation Method 1
the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other to form a PN junction
Implementation Method 2
a first plurality of dopant regions above and in contact with corresponding portions of the sub-fin, the first plurality of dopant regions comprising a first type of dopant; a second plurality of dopant regions above and in contact with corresponding portions of the sub-fin, the second plurality of dopant regions comprising a second type of dopant
Data Source
AI summary
An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.