Sub-Fin Etch Depth Layout for Low-Resistance ESD Conduction
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Solution Overview
Problem
Designing ESD protection devices for integrated circuits is challenging due to the increasing difficulty in forming low resistance contacts with the bulk substrate as gate pitch shrinks, and existing configurations that use the bulk substrate for current conduction are not adaptable when it is removed.
Innovation Solution
The integration of diffusion regions that extend deeply within sub-fins to establish better electrical contact, allowing for more robust current conduction and lower resistance, while maintaining a thicker sub-fin for ESD protection devices compared to logic devices, which do not require significant current conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion regions are extended deeply within sub-fins to establish better electrical contact, then current carrying capability is enhanced and resistance is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extends diffusion regions in the vertical dimension deep within sub-fins rather than only lateral expansion. This vertical extension into the third dimension enables better electrical contact and lower resistance without proportionally increasing lateral device footprint, thereby improving current carrying capability while controlling complexity growth.
Solution Approach 2:
The diffusion regions are nested within the sub-fin structures, with the diffusion regions positioned inside and extending along the sub-fin depth. This nesting arrangement maximizes contact area between diffusion regions and sub-fins, enhancing electrical connection efficiency while utilizing the existing sub-fin geometry to minimize additional structural complexity.
2Reliability
If sub-fins are made thicker for ESD protection devices, then current conduction is improved, but manufacturing precision requirements increase compared to logic devices
Solution Approach 1:
The patent applies different sub-fin thicknesses to different device types within the same integrated circuit. ESD protection devices have thicker sub-fins optimized for current conduction, while logic devices have thinner sub-fins. This local differentiation allows each device type to have optimized dimensions for its specific function, improving current conduction where needed while maintaining manufacturing precision through targeted rather than universal dimensioning.
Solution Approach 2:
The sub-fin thickness parameter is changed based on device function. By adjusting this critical dimension parameter - thicker for ESD devices requiring high current conduction, thinner for logic devices - the patent optimizes performance for each device type. This parameter variation approach enables differentiated performance characteristics while using the same manufacturing process framework.
Data Source
AI summary
An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.