Sub-FPGA Compilation Platform with Adjustable Dynamic Regions
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Solution Overview
Problem
Traditional FPGA-based emulation systems face significant challenges in reducing compile time, which is crucial for efficiently mapping large and complex ASIC designs onto FPGAs, leading to prolonged runtime and increased costs.
Innovation Solution
The implementation of a sub-FPGA level compilation platform with adjustable dynamic regions, utilizing Dynamic Functional Exchange (DFX) technology to partition FPGAs into multiple nested sub-regions, allowing for parallel compilation and optimized routing, thereby reducing compile time and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FPGA-based emulation systems map large ASIC designs onto FPGAs, then design verification capability is improved, but compile time increases significantly
Solution Approach 1:
The patent divides the FPGA device into multiple sub-FPGA regions (e.g., eight sub-regions) and partitions the ASIC design netlist into corresponding sub-netlists. Each sub-netlist is mapped to a specific sub-FPGA region independently, allowing parallel compilation processes that significantly reduce overall compile time while maintaining complete design verification capability.
2Device complexity
If the netlist is partitioned into sub-netlists for mapping to single FPGAs, then mapping complexity is reduced, but the number of FPGAs required increases
Solution Approach 1:
The patent implements a hierarchical region structure where the FPGA is divided into upper-level sub-FPGA regions, which are further divided into lower-level sub-FPGA regions. This nested structure allows sub-netlists to be mapped to appropriate hierarchical levels, reducing the effective number of discrete FPGA devices needed while managing mapping complexity through organized hierarchy.
3Quantity of substance
If larger FPGAs are used to accommodate bigger ASIC designs, then the number of FPGAs per system is reduced, but compile time increases
Solution Approach 1:
Instead of using a single large FPGA which requires sequential compilation of the entire netlist, the patent segments the large FPGA into multiple sub-FPGA regions. Each region can be compiled independently and in parallel, reducing the total compile time even though the same amount of logic is implemented. This maintains the benefit of using fewer physical FPGAs while eliminating the sequential compilation bottleneck.
4Productivity
If the FPGA is divided into fixed sub-FPGA regions, then compilation parallelism is improved, but adaptability to different design sizes is reduced
Solution Approach 1:
The patent implements adjustable dynamic regions within the FPGA structure. The size and configuration of sub-FPGA regions can be dynamically adjusted based on the specific ASIC design being verified. This allows the system to maintain compilation parallelism for different design sizes and complexities by adapting the regional partitioning to match the design requirements, rather than using fixed partitions.
Data Source
AI summary
A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.