Sub-Integer Frequency Divider Using Phase Rotation to Cut Spurs
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Solution Overview
Problem
Conventional fractional-N synthesizers face limitations in achieving precise sub-integer frequency division with minimal phase noise and spurs, particularly in applications requiring tight channel resolution, where existing techniques like dual-modulus dividers and delta-sigma modulators may introduce unwanted frequency components.
Innovation Solution
An electronic sub-integer frequency divider circuit incorporating a phase rotator circuit, clock circuitry, and a pulse generator to produce phase-shifted signals and control signals, allowing for sub-integer division ratios by rotating phase-shift states and adjusting pulse counts within specific periods, thereby generating a sub-integer output signal responsive to a regulating signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional dual-modulus dividers and delta-sigma modulators are used for fractional-N synthesis, then frequency division capability is improved, but phase noise and spurs increase
Solution Approach 1:
The frequency division operation is segmented into integer division and fractional phase rotation components. The circuit performs integer division first, then applies fractional phase rotation to achieve precise sub-integer division ratios without the harmful frequency components generated by conventional switching methods.
Solution Approach 2:
The phase rotator circuit employs periodic phase-shift state transitions synchronized with the divided clock signal. This periodic action at the divided frequency ensures that phase adjustments occur at consistent intervals, eliminating random phase noise and periodic spurs.
2Measurement precision
If tight channel resolution is required, then frequency precision is improved, but circuit complexity increases
Solution Approach 1:
The circuit transitions from time-domain frequency switching to phase-domain rotation. By representing frequency ratios as phase shifts (0 to 360 degrees), the system achieves fine frequency resolution through continuous phase adjustment rather than complex multi-modulus switching, simplifying the overall circuit architecture.
3Speed
If loop bandwidth is increased, then frequency synthesis speed is improved, but phase noise amplification increases
Solution Approach 1:
The patent replaces the mechanical switching approach of conventional fractional-N dividers with an electronic phase rotation mechanism. This substitution enables smoother phase transitions and reduces switching transients that contribute to phase noise, allowing wider loop bandwidths without excessive noise amplification.
Data Source
AI summary
An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.