Sub-ISA Processor Generation for Lower Area and Power
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Solution Overview
Problem
Existing methods for designing sub-ISA processors are cumbersome and inefficient, failing to significantly reduce silicon area or power consumption due to the difficulty in modifying HDL descriptions to support only a subset of instructions, as conventional approaches typically involve subtracting gates from full ISA designs.
Innovation Solution
A method to generate a sub-ISA processor by selecting a subset of instructions from a full ISA, retrieving hardware representations from a library, and generating a fabrication technology-independent RTL representation in HDL, which is then synthesized for specific technologies, allowing for a bespoke processor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional method of subtracting gates from full ISA designs is used, then the design process is straightforward, but the silicon area and power consumption are not significantly reduced
Solution Approach 1:
The patent segments the instruction set into a library of individual instruction representations, each with its own hardware implementation. This allows selective combination of only the required instructions for a sub-ISA, rather than subtracting from a full ISA design. The segmentation enables modular assembly of processor components based on actual requirements.
Solution Approach 2:
Instead of starting with a full ISA design and subtracting unnecessary instructions (conventional approach), the patent inverts the approach by starting with a library of individual instructions and selectively combining only the required ones to build the sub-ISA. This inversion enables more effective reduction of silicon area and power consumption.
2Use of energy by stationary object
If HDL descriptions are modified to support only a subset of instructions, then power consumption is reduced, but the modification process is very difficult
Solution Approach 1:
The patent performs preliminary action by pre-generating and storing hardware representations of individual instructions in a library before the actual sub-ISA design is needed. This library serves as a ready-to-use resource that simplifies the subsequent process of creating sub-ISA designs, as the hardware representations are already prepared and can be selectively retrieved and combined.
Solution Approach 2:
The patent introduces an intermediary library of instruction representations that mediates between the full ISA specification and the desired sub-ISA implementation. This intermediary layer allows easy selection and combination of individual instructions without requiring direct modification of complex HDL descriptions, thereby reducing power consumption while simplifying the design process.
3Adaptability or versatility
If a full ISA is designed to support all instructions, then the processor is versatile, but the silicon area and power consumption are high
Solution Approach 1:
The patent applies partial action by implementing only the subset of instructions actually required for a specific application or domain, rather than implementing the full ISA. The library approach allows selective inclusion of instructions based on actual needs, achieving adequate versatility for the intended purpose while significantly reducing silicon area and power consumption.
Solution Approach 2:
The patent applies local quality by tailoring the instruction set and hardware implementation to the specific requirements of different applications or domains. Each sub-ISA can be optimized for its intended purpose by selecting and combining only the relevant instructions from the library, creating locally optimized processors with appropriate versatility for their specific use cases.
Data Source
AI summary
A method of generating a design for a processor in accordance with a subset instruction set architecture is disclosed in which a subset of one or more instructions, from a set of instructions for an instruction set architecture is obtained. A representation of hardware for implementing each instruction of the subset is retrieved from a library that includes a representation of hardware for implementing each instruction of the set of instructions. A further representation of hardware for implementing the processor in accordance with the subset instruction set architecture is generated using the retrieved representations of hardware for implementing the instructions of the subset.