Sub-lithographic Transistors via Block Copolymer Self-Assembly
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional lithographic techniques limit the scaling of transistor gate lengths below 60 nm, leading to increased line edge roughness and critical dimension variations, which result in threshold voltage fluctuations and reduced process window in semiconductor devices.
Innovation Solution
A method using self-assembling block copolymers, combined with conventional lithographic technology, to form sub-lithographic transistors by selectively removing polymer components and using the remaining polymer as a mask to pattern transistor gates, avoiding line edge roughness and CD variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic techniques are used to pattern transistor gates, then manufacturing process is simple and well-established, but gate length cannot be scaled below 60 nm and line edge roughness increases
Solution Approach 1:
The patterning process is segmented into two stages: conventional lithography creates a relaxed hard mask pattern, then block copolymer self-assembly creates the final sub-lithographic pattern within each hard mask region. This segmentation allows the final gate length to be determined by polymer physics rather than lithographic resolution limits.
Solution Approach 2:
The hard mask pattern is formed in advance using conventional lithography with larger dimensions, providing a template that guides subsequent block copolymer self-assembly. This preliminary action defines the approximate gate locations and spacing before the final sub-lithographic patterning occurs.
2Productivity
If transistor gate length is scaled down to improve device density, then device density increases, but line edge roughness and critical dimension variation increase
Solution Approach 1:
The block copolymer system performs self-service by automatically forming patterns with sub-lithographic precision through spontaneous self-assembly. The polymer molecules self-organize into domains with controlled dimensions and spacing, eliminating the need for high-precision lithographic alignment and reducing line edge roughness.
Solution Approach 2:
The critical dimension control mechanism changes from lithographic parameters (wavelength, numerical aperture) to polymer parameters (molecular weight, composition, self-assembly morphology). By adjusting block copolymer composition and processing conditions, the gate length and line edge roughness are controlled through material properties rather than optical parameters.
3Length of moving object
If conventional lithography is used to achieve smaller gate lengths, then feature size decreases, but critical dimension variation and threshold voltage fluctuation increase
Solution Approach 1:
The mechanical/optical lithographic system is replaced with a chemical self-assembly system. Instead of using light to define patterns, the patent uses block copolymer thermodynamics and self-organization to spontaneously form patterns with controlled dimensions. This substitution eliminates optical diffraction limits and associated critical dimension variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of transistors with sub-lithographic gate lengths of less than 60 nm, reducing line edge roughness and improving device performance by determining feature size through polymer molecule alignment rather than conventional lithography.
Implementation Method 1
a self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern
Data Source
AI summary
A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.