Sub-mapping Table Allocation in DRAM-less Storage

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Solution Overview

Problem

Data storage devices without dynamic random access memory (DRAM) face performance issues due to the limited capacity of static random access memory (SRAM), necessitating an effective memory management method to enhance performance.

Innovation Solution

A memory management method that requests a private memory space from a host, divides the mapping table into sub-mapping tables, and allocates them to either the reserved memory space or partitions it into dynamic and static memory spaces based on capacity, using interface logic to upload tables accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dynamic random access memory (DRAM) is employed to increase memory capacity, then performance is improved, but hardware cost increases

Engineering Contradiction:
ImproveperformanceVSAvoidhardware cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent introduces an external memory device as an intermediary component between the controller and the host. This external memory acts as a buffer to store mapping tables, allowing the controller to use smaller, cheaper SRAM while maintaining high performance through fast access to mapping data via the NVLink interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If static random access memory (SRAM) capacity is increased to improve performance, then performance is improved, but hardware cost and device complexity increase

Engineering Contradiction:
ImproveperformanceVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the mapping table storage function across multiple components: a small portion is stored in SRAM within the controller for frequently accessed data, while the majority is stored in external memory. This segmentation allows the controller to maintain low complexity while achieving high performance through coordinated access to both memory types.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If SRAM capacity is kept small to reduce hardware cost, then hardware cost is reduced, but performance deteriorates

Engineering Contradiction:
Improvehardware costVSAvoidperformance
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent adds a new dimension to the memory hierarchy by introducing external memory connected through a high-speed NVLink interface. This creates a multi-layered memory architecture where small, fast SRAM handles immediate needs while large-capacity external memory provides extensive storage, achieving both cost-effectiveness and high performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11455241B2Data management method applicable to data storage device
Publication Date: 2022.09.27 SILICON MOTION INC
  • US11455241B2 patent drawing
  • US11455241B2 patent drawing
  • US11455241B2 patent drawing

AI summary

A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.