Sub-Memory Array Layout With Overlapping Local Sense Amplifiers
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Solution Overview
Problem
Existing memory devices face challenges in efficiently arranging word line drivers and sense amplifier circuits due to irregularly sized independent cell arrays, leading to increased device size and reduced memory reliability and productivity.
Innovation Solution
A memory device with a cell on peripheral (COP) structure, featuring a memory cell region with sub-memory arrays and a peripheral circuit region that overlaps these arrays in orthogonal directions, utilizing local sense amplifier circuits connected to bit lines to optimize area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent cell arrays of irregular sizes are used to increase memory reliability and productivity, then memory reliability and productivity are improved, but the overall device size increases due to inefficient arrangement of word line drivers and sense amplifier circuits
Solution Approach 1:
The patent merges the arrangement of word line drivers and sense amplifier circuits into a unified peripheral circuit region that efficiently serves multiple sub-memory arrays of irregular sizes. This consolidation reduces the overall device area by eliminating redundant circuit elements and optimizing the shared infrastructure across different cell array sizes.
Solution Approach 2:
The peripheral circuit region is designed with universal word line drivers and sense amplifier circuits that can serve multiple sub-memory arrays with different sizes. This multi-functional design allows the same circuit infrastructure to support variable array configurations, reducing the need for dedicated circuits for each array and thereby minimizing device area.
2Reliability
If independent cell arrays of irregular sizes are used to increase memory reliability and productivity, then memory reliability and productivity are improved, but the arrangement of word line drivers and sense amplifier circuits becomes complex and inefficient
Solution Approach 1:
The patent segments the memory device into a regular memory cell region and a separate peripheral circuit region. This segmentation allows the complex word line drivers and sense amplifier circuits to be organized in a dedicated area with systematic interconnections to multiple sub-memory arrays, reducing the overall structural complexity compared to distributed arrangements.
Solution Approach 2:
The patent resolves arrangement complexity by transitioning from a two-dimensional planar distribution of circuits to each array to a three-dimensional layout where peripheral circuits are concentrated in a dedicated region that spatially overlaps with the memory cell region. This dimensional reorganization simplifies the interconnection topology and reduces routing complexity.
3Ease of manufacture
If peripheral circuits are arranged separately from memory cell arrays, then circuit layout is simplified, but area efficiency is reduced due to increased device size
Solution Approach 1:
The patent implements a nested structure where the peripheral circuit region is positioned to spatially overlap with the memory cell region in the planar layout. This nesting allows peripheral circuits to be manufactured with simplified layout processes while occupying the same footprint area, thereby maintaining area efficiency without compromising manufacturing simplicity.
Data Source
AI summary
A memory device is provided. The memory device includes a memory cell region including a first sub-memory array and a second sub-memory array arranged in a first direction, and a peripheral circuit region including a first local sense amplifier circuit that at least partially overlaps the first and second sub-memory arrays in a second direction. The first sub-memory array includes first volatile memory cells electrically connected to a first word line and to respective ones of first bit lines. The second sub-memory array includes second volatile memory cells electrically connected to a second word line and to respective ones of second bit lines. The first local sense amplifier circuit is electrically connected to at least one of the first bit lines and to at least one of the second bit lines. A number of the first bit lines is equal to a number of the second bit lines.