Sub-Package Semiconductor Layout for Thin High-Capacity Packaging
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Solution Overview
Problem
The increasing performance demands of semiconductor devices lead to increased size and power consumption, which impedes miniaturization and affects reliability.
Innovation Solution
A semiconductor package design featuring a centrally disposed controller chip buried in a high-thermal-conductivity sealant, with vertically stacked chip towers on either side, optimized routing, and a redistribution wiring layer for improved heat dissipation and reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If expanded performance requirements are implemented to meet user demands, then functionality and data storage capacity are improved, but package size and thickness increase
Solution Approach 1:
The patent transitions from horizontal expansion to vertical stacking by implementing multi-layer chip structures stacked in the thickness direction. This dimensional change allows increased storage capacity without proportionally increasing package footprint, effectively addressing the contradiction between capacity and thickness
Solution Approach 2:
The patent employs a nested structure where multiple chip layers are stacked within a compact package footprint. The controller chip, memory chips, and buffer chips are arranged in vertical layers, with each layer containing multiple chips that are nested within the overall package structure, maximizing space utilization
2Quantity of substance
If expanded performance requirements are implemented, then functionality is improved, but power consumption increases
Solution Approach 1:
The patent divides the system into functionally segmented modules: controller chips for management, memory chips for storage, and buffer chips for data temporary storage. This segmentation allows selective activation of components based on operational needs, reducing overall power consumption while maintaining required storage capacity
Solution Approach 2:
The patent introduces buffer chips as intermediary elements between the controller and memory chips. These buffers temporarily hold data, reducing the frequency of active data transfer operations and thereby lowering the power consumption of the overall system while maintaining high storage capacity
3Quantity of substance
If package size is increased to meet performance demands, then functionality is improved, but miniaturization efforts are impeded
Solution Approach 1:
The patent utilizes the vertical dimension for scaling by implementing multi-layer stacking architectures. Instead of increasing package footprint horizontally, the design stacks multiple chip layers in the thickness direction, enabling capacity expansion with minimal volume increase
Solution Approach 2:
The patent combines multiple functional chips (controller, memory, buffer) into a single integrated package structure. By merging these components into a unified stacked architecture, the patent achieves high storage capacity within a compact volume, preventing package bloat while meeting performance requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a reduced thickness of less than 1.0 mm, enhanced heat dissipation, and improved power handling, while maintaining high performance and reliability.
Implementation Method 1
a controller chip buried in a high-thermal-conductivity sealant
Data Source
AI summary
A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.