Sub-page-granular Cache Coherency via Sparse Virtual Memory
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Solution Overview
Problem
Conventional shared memory systems face inefficiencies in data access and contention due to page-granular and cache-line-granular data-sharing approaches, which lead to high resource consumption and reliability issues, particularly in handling small data modifications and creating single fault domains.
Innovation Solution
The technique leverages enhanced standard virtual memory mechanisms to access shared data at a sub-page level using sparse virtual pages, minimizing memory access contention and improving latency through atomic remote direct memory access and page fault handler enhancements, avoiding the need for costly hardware implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If page-granular data-sharing approach is used, then data sharing between nodes is enabled, but memory access contention increases and system resources are consumed due to back-and-forth transfers
Solution Approach 1:
The patent segments the shared memory space into sub-page granular regions, allowing different portions of a page to be independently accessed by different nodes. This segmentation enables fine-grained access control where only the specific sub-region being modified needs to be transferred, rather than the entire page, thus reducing memory access contention and improving system productivity while maintaining data sharing capability
Solution Approach 2:
The patent implements local quality by allowing each node to have its own local copy of frequently accessed shared data in its cache memory, while maintaining the ability to access remote copies when needed. This approach optimizes local access speed while preserving remote data sharing capabilities, resolving the contradiction between data sharing versatility and access efficiency
2Productivity
If cache-line-granular data-sharing approach is used, then memory access contention is reduced, but hardware complexity increases and reliability decreases due to single fault domain
Solution Approach 1:
The patent replaces complex hardware-based cache coherence management with software-based virtual memory mechanisms. By using the operating system's page fault handler and virtual memory subsystem to manage shared memory access, the system achieves cache-line-granular efficiency without requiring complex hardware logic on each node, thus reducing device complexity while maintaining productivity
Solution Approach 2:
The patent makes the virtual memory subsystem universal by using the same OS-level mechanisms that already exist for local memory management to also handle shared remote memory. This multi-functionality allows a single software-based solution to replace multiple specialized hardware components, reducing overall system complexity while maintaining efficient memory access
3Reliability
If page-granular locking mechanism is used, then data coherency is maintained, but access latency increases due to waiting for lock release
Solution Approach 1:
The patent segments the locking mechanism to operate at the sub-page granular level rather than the entire page level. This allows multiple nodes to simultaneously hold locks on different sub-regions of the same page, enabling concurrent access to unrelated data portions. This segmentation maintains data coherency within each locked region while significantly reducing access latency by eliminating unnecessary waiting for lock release
Solution Approach 2:
The patent applies partial locking by acquiring locks only on the specific sub-regions that need to be accessed or modified, rather than locking the entire page. This partial action approach maintains coherency for the accessed regions while leaving other regions available for concurrent access, thus reducing access latency without compromising data coherency reliability
Data Source
AI summary
A technique involves providing access to shared data based on enhanced standard virtual memory mechanisms. Once data from a shared area of memory is moved into primary memory of a first computerized device from a second computerized device, the first computerized device can retain that data in order to shorten the latency of subsequent accesses. Such a technique can be configured to handle shared data at the sub-page-granular level using sparse virtual pages to minimize memory access contention and thus improve the likelihood of quick re-hits. Furthermore, such a technique can be conveniently accomplished through an enhancement to a common page fault handler of an operating system and utilizing atomic remote access support from a standard communications protocol thus alleviating the need to employ more costly and complicated solutions such as inflexible hardware implementations or independent programs that could pose additional design burdens and reliability concerns.