Sub-Radix-2 SAR ADC for Comparator Offset-Tolerant Image Readout
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Solution Overview
Problem
Conventional charge sharing SAR analog-to-digital converters (ADCs) in image sensors are limited to less than 10 bits of resolution due to sensitivity to comparator offset, which cannot be effectively mitigated by existing calibration techniques.
Innovation Solution
Implementing a sub-radix-2 capacitor scaling scheme in the digital-to-analog converter (DAC) of the SAR ADC, where capacitors are sized with a scaling factor less than 2, providing redundancy and reducing sensitivity to comparator offset, allowing for resolutions beyond 10 bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional charge sharing SAR ADC is used, then the conversion speed is fast, but the resolution is limited to less than 10 bits due to comparator offset sensitivity
Solution Approach 1:
The patent changes the capacitor scaling parameter from conventional radix-2 (factor of 2) to sub-radix-2 (factor less than 2, e.g., 1.9). This parameter change creates redundancy in the capacitor array that provides tolerance to comparator offset, enabling resolutions of 10 bits or more while maintaining the fast conversion speed of charge sharing SAR ADC architecture
Solution Approach 2:
The patent applies beforehand cushioning by designing the capacitor array with sub-radix-2 scaling that inherently provides a margin or buffer against comparator offset errors. This redundancy is built into the architecture in advance, allowing the system to tolerate offset variations without degrading resolution performance
2Measurement precision
If radix-2 capacitor scaling is used in charge sharing SAR ADC, then the device complexity is low, but the measurement precision is limited to less than 10 bits
Solution Approach 1:
The patent modifies the capacitor scaling parameter from radix-2 to sub-radix-2, which provides the necessary redundancy for high-resolution conversion. While this changes the capacitor values, it maintains a regular array structure that does not significantly increase device complexity, achieving 10-bit or higher resolution with manageable complexity
Data Source
AI summary
An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.