Sub-Range ADC Architecture for Timing and Phase Error Resistance
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Solution Overview
Problem
Modern communication devices face challenges in sampling analog communication signals across wide frequency bands using a single Analog to Digital Converter (ADC), leading to timing and phase errors, which are exacerbated in powerline communication systems, and result in increased size, power consumption, and heat generation due to required correction circuits.
Innovation Solution
The implementation of a multi-sub-range ADC structure with a central sub-range ADC having higher quantization accuracy and smaller quantization step size, combined with signal combining circuitry to produce a digital communication signal, reduces the impact of timing and phase errors and improves resistance to impulse noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple individual ADCs are combined to sample wide frequency bands, then the frequency band coverage is improved, but timing and phase errors increase
Solution Approach 1:
The patent divides the wide frequency band into multiple sub-ranges, with each sub-range handled by a dedicated ADC. This segmentation allows each ADC to operate within a narrower, optimized frequency range, reducing timing and phase errors while maintaining overall wide band coverage through coordinated operation of multiple ADCs.
2Reliability
If timing and phase error correction circuits are added, then timing and phase errors are reduced, but device size and power consumption increase
Solution Approach 1:
The patent performs timing and phase alignment in advance during the signal processing pipeline, before final conversion and output. By pre-aligning the signals from multiple ADCs, the system reduces the need for complex real-time correction circuits, thereby lowering device size and power consumption while maintaining reliability.
3Adaptability or versatility
If multiple ADCs are used in time divided manner, then wide frequency band sampling is achieved, but timing synchronization becomes more problematic
Solution Approach 1:
The patent implements feedback mechanisms where the system continuously monitors and adjusts the timing and phase of each ADC based on reference signals and performance metrics. This feedback loop enables dynamic timing synchronization, ensuring that multiple ADCs operating in a time-divided manner remain precisely coordinated across the wide frequency band.
4Reliability
If correction circuits are implemented, then timing errors are reduced, but heat generation and power consumption increase
Solution Approach 1:
The patent optimizes operating parameters such as sampling rates, clock frequencies, and signal processing gains to achieve timing error reduction without requiring excessive power-consuming correction circuits. By carefully tuning these parameters, the system maintains high reliability while minimizing energy loss and heat generation.
Data Source
AI summary
An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.