Sub-Ranging ADC Partial Time-Interleaving for Lower Power
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Solution Overview
Problem
Conventional sub-ranging analog-to-digital converters (ADCs) require high-powered components for coarse and fine conversion operations, leading to high costs and power consumption, and the time-interleaved architecture with multiple DACs and comparators increases area and power usage on system-on-chip (SoC).
Innovation Solution
A sub-ranging ADC design that utilizes multiple DACs and converters in a partially time-interleaved architecture, where fine conversion is performed over one or more cycles of the clock signal, reducing the need for high-powered fine ADCs and optimizing the number of converters to minimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple sub-ADCs are implemented in a time-interleaved architecture, then conversion speed is improved, but area consumption and power usage increase
Solution Approach 1:
The fine ADC is segmented into multiple DACs (first through third DACs) that operate in non-overlapping time intervals, allowing the conversion function to be divided across multiple components that share resources. This segmentation enables higher effective conversion speed while reducing the area required compared to having all DACs simultaneously active.
Solution Approach 2:
The DACs are configured to receive the analog input signal for non-overlapping durations of the clock signal, creating a periodic time-interleaved operation pattern. This periodic activation allows the system to achieve higher average conversion speed while reducing instantaneous power consumption and area requirements, as not all DACs need to be fully equipped and active simultaneously.
2Speed
If multiple DACs and conversion circuits are implemented in a time-interleaved architecture, then conversion speed is improved, but the number of high-powered comparators increases power consumption
Solution Approach 1:
The first converter is designed to handle multiple functions by converting analog output signals from multiple DACs (first and second DACs) at different time intervals. This multi-functional converter design reduces the total number of high-powered comparators needed, as one converter serves multiple DACs rather than requiring dedicated converters for each DAC, thereby reducing overall power consumption.
Solution Approach 2:
The system discards the need for simultaneous operation of all conversion circuits by using time-interleaved operation. The third DAC operates in a sixth duration that partially overlaps with other durations, allowing for more efficient resource utilization and reduced power consumption by activating conversion circuits only when needed rather than maintaining all circuits in high-power states continuously.
3Measurement precision
If high-powered coarse and fine ADCs are employed to perform conversion operations in half cycle, then conversion precision is maintained, but cost and power consumption increase
Solution Approach 1:
The system uses dynamic time-interleaved operation where DACs and converters are activated in different time intervals rather than requiring all components to operate simultaneously at full power. This dynamic operation allows the use of less powerful, lower-cost components that can handle their specific time slots, reducing overall system cost while maintaining conversion precision through coordinated operation across multiple cycles.
Data Source
AI summary
A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.