Sub-Ranging ADC Pipeline With Non-Overlapping Coarse and Fine Conversion
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Solution Overview
Problem
Conventional sub-ranging ADCs face limitations in conversion speed and power consumption due to overlapping phases of coarse and fine conversions, which affect the resolution and efficiency of digital output signals.
Innovation Solution
Implementing a sub-ranging ADC with dedicated phases for coarse and fine conversions, utilizing multiple DACs in a pipeline architecture to operate in parallel without overlap, allowing for non-overlapping clock cycles and improved resolution and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If coarse and fine conversions are performed in a single phase of the ADC conversion cycle, then the device complexity is reduced, but the conversion speed decreases and power consumption increases
Solution Approach 1:
The ADC conversion process is segmented into distinct phases: a first phase for coarse conversion by the flash ADC and a second phase for fine conversion by the SAR ADC. This temporal segmentation allows each converter to operate with dedicated resources and timing, improving overall conversion speed while managing complexity through structured phase separation.
Solution Approach 2:
The ADC operates using periodic clock cycles that are divided into phases. The first clock cycle is dedicated to coarse conversion, and the second clock cycle is dedicated to fine conversion. This periodic phasing allows for optimized timing and resource allocation in each phase, enhancing conversion speed without requiring all components to operate simultaneously.
2Device complexity
If coarse and fine conversions are performed in a single phase of the ADC conversion cycle, then the device complexity is reduced, but power consumption increases
Solution Approach 1:
The conversion process is segmented into separate phases for coarse and fine conversions. During the first phase, only the flash ADC and its associated components are active, consuming power selectively. During the second phase, the SAR ADC becomes active while the flash ADC remains inactive. This temporal segmentation reduces overall power consumption compared to having all components active simultaneously in a single phase.
Solution Approach 2:
Power is consumed periodically in distinct phases rather than continuously. The first phase activates power-intensive flash ADC components for coarse conversion, then these components are deactivated. The second phase activates the SAR ADC for fine conversion. This periodic activation pattern reduces average power consumption while maintaining functional complexity.
Data Source
AI summary
A sub-ranging analog-to-digital converter (ADC) converts an analog input signal to a digital output signal. The sub-ranging ADC includes a coarse ADC, a fine ADC, and an error correction circuit (ECC). The fine ADC includes at least three digital-to-analog converters (DACs) that are connected in a pipeline architecture. The coarse and fine ADCs receive the analog input signal in a first half cycle of a clock signal. The coarse ADC converts the analog input signal to a first digital signal in a second half cycle of the clock signal. At least one of the first through third DACs converts the analog input signal to a second digital signal in a full cycle of the clock signal. The ECC receives the first and second digital signals and generates the digital output signal.