Sub-Ranging TDC Clock Screening for Wide-Range Jitter Measurement
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Solution Overview
Problem
Conventional clock screening techniques fail to provide a unified solution for high-resolution, wide-input-frequency-range clock performance measurements due to high power consumption and sensitivity to process variations, leading to false results.
Innovation Solution
A sub-ranging time-to-digital converter (TDC) that measures time differences using a combination of slow and fast oscillators with coarse and fine counters, integrated into a clock measurement circuit for multiple clock performance metrics, including period jitter, K-cycle jitter, duty cycle, and clock skew, while being robust to process variations and power supply fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional flash TDC or Vernier TDC architectures use numerous delay cells to achieve high resolution and wide input frequency range, then measurement precision is improved, but chip area and power consumption increase substantially
Solution Approach 1:
The patent segments the time measurement function into two distinct parts: a coarse TDC for measuring large time intervals and a fine TDC for measuring small time intervals. This segmentation allows each TDC to be optimized independently, reducing the total number of delay cells required while maintaining high measurement precision across a wide frequency range.
Solution Approach 2:
The patent introduces a dual-Time-to-Digital Converter architecture that operates in two dimensions: coarse measurement dimension and fine measurement dimension. By combining measurements from both dimensions, the system achieves high resolution without requiring a single large-scale TDC, thus reducing chip area.
2Measurement precision
If conventional flash TDC or Vernier TDC architectures use numerous delay cells to achieve high resolution and wide input frequency range, then measurement precision is improved, but power consumption increases substantially
Solution Approach 1:
By dividing the TDC into coarse and fine segments, the patent reduces the total number of active delay cells at any given time. The coarse TDC handles large time intervals with fewer cells, while the fine TDC handles small intervals with higher precision, collectively reducing power consumption while maintaining measurement precision.
Solution Approach 2:
The patent employs partial action by activating only the necessary TDC component (coarse or fine) based on the input signal characteristics. This selective activation reduces power consumption compared to having all delay cells continuously active in a single large TDC architecture.
3Measurement precision
If a plurality of delay cells is used to meet high resolution and wide input frequency range requirements, then measurement capability is improved, but process variation sensitivity increases leading to lower testing robustness
Solution Approach 1:
The patent segments the measurement function into coarse and fine TDCs, where each segment uses a limited number of delay cells. This reduces the cumulative effect of process variations across numerous cells, improving testing robustness while maintaining measurement precision through the coordinated operation of both segments.
Solution Approach 2:
The patent implements a feedback mechanism where the coarse TDC measurement results are used to control the operation of the fine TDC. This feedback loop allows the system to compensate for process variations by dynamically adjusting the fine measurement based on the coarse measurement, thereby improving reliability.
4Adaptability or versatility
If a unified clock performance screening circuit is designed to simultaneously support high resolution, wide input frequency range, and high robustness, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the unified clock performance screening circuit into distinct coarse and fine measurement paths, each optimized for specific measurement ranges. This segmentation allows the circuit to support multiple measurement modes (high resolution, wide frequency range, high robustness) without requiring a single complex monolithic structure, thereby managing device complexity.
Solution Approach 2:
The patent creates a universal clock measurement circuit that can perform multiple measurement functions (period jitter, duty cycle, clock skew, etc.) through the coordinated operation of the coarse and fine TDCs. This multi-functionality is achieved without proportionally increasing complexity, as both TDCs share common control and processing resources.
Data Source
AI summary
A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.